Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7358146 [patent_doc_number] => 20040090809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Memory device array having a pair of magnetic bits sharing a common conductor line' [patent_app_type] => new [patent_app_number] => 10/692617 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4015 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090809.pdf [firstpage_image] =>[orig_patent_app_number] => 10692617 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/692617
Memory device array having a pair of magnetic bits sharing a common conductor line Oct 23, 2003 Issued
Array ( [id] => 758778 [patent_doc_number] => 07020035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Measuring and correcting sense amplifier and memory mismatches using NBTI' [patent_app_type] => utility [patent_app_number] => 10/683633 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5947 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020035.pdf [firstpage_image] =>[orig_patent_app_number] => 10683633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683633
Measuring and correcting sense amplifier and memory mismatches using NBTI Oct 9, 2003 Issued
Array ( [id] => 7225812 [patent_doc_number] => 20050078527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Method of over-erase prevention in a non-volatile memory device and related structure' [patent_app_type] => utility [patent_app_number] => 10/683304 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4917 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20050078527.pdf [firstpage_image] =>[orig_patent_app_number] => 10683304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683304
Method of over-erase prevention in a non-volatile memory device and related structure Oct 9, 2003 Issued
Array ( [id] => 7440817 [patent_doc_number] => 20040066672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Vertical NROM having a storage density of 1 bit per IF2' [patent_app_type] => new [patent_app_number] => 10/681408 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10025 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066672.pdf [firstpage_image] =>[orig_patent_app_number] => 10681408 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681408
Vertical NROM having a storage density of 1 bit per 1F2 Oct 7, 2003 Issued
Array ( [id] => 758650 [patent_doc_number] => 07019999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Content addressable memory with latching sense amplifier' [patent_app_type] => utility [patent_app_number] => 10/681525 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 13051 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019999.pdf [firstpage_image] =>[orig_patent_app_number] => 10681525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681525
Content addressable memory with latching sense amplifier Oct 7, 2003 Issued
Array ( [id] => 7420985 [patent_doc_number] => 20040160798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Adaptive programming technique for a re-writable conductive memory device' [patent_app_type] => new [patent_app_number] => 10/680508 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7753 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160798.pdf [firstpage_image] =>[orig_patent_app_number] => 10680508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680508
Adaptive programming technique for a re-writable conductive memory device Oct 5, 2003 Issued
Array ( [id] => 977289 [patent_doc_number] => 06934182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method to improve cache capacity of SOI and bulk' [patent_app_type] => utility [patent_app_number] => 10/678508 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5383 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934182.pdf [firstpage_image] =>[orig_patent_app_number] => 10678508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/678508
Method to improve cache capacity of SOI and bulk Oct 2, 2003 Issued
Array ( [id] => 7376534 [patent_doc_number] => 20040080971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/676110 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9641 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080971.pdf [firstpage_image] =>[orig_patent_app_number] => 10676110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676110
Semiconductor memory device using open data line arrangement Oct 1, 2003 Issued
Array ( [id] => 7614414 [patent_doc_number] => 06898116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection' [patent_app_type] => utility [patent_app_number] => 10/677613 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 7092 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898116.pdf [firstpage_image] =>[orig_patent_app_number] => 10677613 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677613
High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection Oct 1, 2003 Issued
Array ( [id] => 7115525 [patent_doc_number] => 20050068826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'SELECTIVE BANK REFRESH' [patent_app_type] => utility [patent_app_number] => 10/674905 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2483 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068826.pdf [firstpage_image] =>[orig_patent_app_number] => 10674905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674905
Selective bank refresh Sep 29, 2003 Issued
Array ( [id] => 7225677 [patent_doc_number] => 20050078500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Backside of chip implementation of redundancy fuses and contact pads' [patent_app_type] => utility [patent_app_number] => 10/674304 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2523 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20050078500.pdf [firstpage_image] =>[orig_patent_app_number] => 10674304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674304
Backside of chip implementation of redundancy fuses and contact pads Sep 29, 2003 Issued
Array ( [id] => 7009497 [patent_doc_number] => 20050063213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Signal margin test mode for FeRAM with ferroelectric reference capacitor' [patent_app_type] => utility [patent_app_number] => 10/665402 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8468 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063213.pdf [firstpage_image] =>[orig_patent_app_number] => 10665402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665402
Signal margin test mode for FeRAM with ferroelectric reference capacitor Sep 17, 2003 Abandoned
Array ( [id] => 1057933 [patent_doc_number] => 06856547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Circuit for biasing an input node of a sense amplifier with a pre-charge stage' [patent_app_type] => utility [patent_app_number] => 10/664606 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856547.pdf [firstpage_image] =>[orig_patent_app_number] => 10664606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/664606
Circuit for biasing an input node of a sense amplifier with a pre-charge stage Sep 15, 2003 Issued
Array ( [id] => 7440879 [patent_doc_number] => 20040066678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF)' [patent_app_type] => new [patent_app_number] => 10/660802 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2701 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066678.pdf [firstpage_image] =>[orig_patent_app_number] => 10660802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/660802
Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF) Sep 11, 2003 Issued
Array ( [id] => 1145131 [patent_doc_number] => 06781866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Semiconductor memory and writing method and reading method for the same' [patent_app_type] => B2 [patent_app_number] => 10/654904 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6425 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781866.pdf [firstpage_image] =>[orig_patent_app_number] => 10654904 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654904
Semiconductor memory and writing method and reading method for the same Sep 4, 2003 Issued
Array ( [id] => 977354 [patent_doc_number] => 06934215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/656303 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4632 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934215.pdf [firstpage_image] =>[orig_patent_app_number] => 10656303 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/656303
Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device Sep 3, 2003 Issued
Array ( [id] => 7293511 [patent_doc_number] => 20040213063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Driving voltage controller of sense amplifiers for memory device' [patent_app_type] => new [patent_app_number] => 10/655204 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2406 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213063.pdf [firstpage_image] =>[orig_patent_app_number] => 10655204 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/655204
Driving voltage controller of sense amplifiers for memory device Sep 3, 2003 Issued
Array ( [id] => 7628764 [patent_doc_number] => 06819596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Semiconductor memory device with test mode' [patent_app_type] => B2 [patent_app_number] => 10/653260 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 15394 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819596.pdf [firstpage_image] =>[orig_patent_app_number] => 10653260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653260
Semiconductor memory device with test mode Sep 2, 2003 Issued
Array ( [id] => 1095541 [patent_doc_number] => 06826068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Fast data readout semiconductor storage apparatus' [patent_app_type] => B1 [patent_app_number] => 10/654463 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 6321 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 500 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826068.pdf [firstpage_image] =>[orig_patent_app_number] => 10654463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654463
Fast data readout semiconductor storage apparatus Sep 2, 2003 Issued
Array ( [id] => 1061279 [patent_doc_number] => 06853576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Semiconductor device, method for fabricating the same, and method for driving the same' [patent_app_type] => utility [patent_app_number] => 10/653201 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 14632 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853576.pdf [firstpage_image] =>[orig_patent_app_number] => 10653201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653201
Semiconductor device, method for fabricating the same, and method for driving the same Sep 2, 2003 Issued
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