Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7358301 [patent_doc_number] => 20040090833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Read-out circuit for a dynamic memory circuit, memory cell array, and method for amplifying and reading data stored in a memory cell array' [patent_app_type] => new [patent_app_number] => 10/653652 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6612 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090833.pdf [firstpage_image] =>[orig_patent_app_number] => 10653652 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653652
Read-out circuit for a dynamic memory circuit, memory cell array, and method for amplifying and reading data stored in a memory cell array Sep 1, 2003 Issued
Array ( [id] => 7315848 [patent_doc_number] => 20040223384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Semiconductor memory device and test method thereof' [patent_app_type] => new [patent_app_number] => 10/653606 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9198 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20040223384.pdf [firstpage_image] =>[orig_patent_app_number] => 10653606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653606
Semiconductor memory device and test method thereof Sep 1, 2003 Issued
Array ( [id] => 997777 [patent_doc_number] => 06914796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Semiconductor memory element with direct connection of the I/Os to the array logic' [patent_app_type] => utility [patent_app_number] => 10/651804 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5234 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914796.pdf [firstpage_image] =>[orig_patent_app_number] => 10651804 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651804
Semiconductor memory element with direct connection of the I/Os to the array logic Aug 28, 2003 Issued
Array ( [id] => 7131829 [patent_doc_number] => 20040042282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method of reducing standby current during power down mode' [patent_app_type] => new [patent_app_number] => 10/649627 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2943 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042282.pdf [firstpage_image] =>[orig_patent_app_number] => 10649627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649627
Method of reducing standby current during power down mode Aug 27, 2003 Issued
Array ( [id] => 1135700 [patent_doc_number] => 06788591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch' [patent_app_type] => B1 [patent_app_number] => 10/604909 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4177 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788591.pdf [firstpage_image] =>[orig_patent_app_number] => 10604909 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604909
System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch Aug 25, 2003 Issued
Array ( [id] => 7441040 [patent_doc_number] => 20040066692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Multi-valued nonvolatile semiconductor storage' [patent_app_type] => new [patent_app_number] => 10/468007 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4922 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066692.pdf [firstpage_image] =>[orig_patent_app_number] => 10468007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/468007
Multi-valued nonvolatile semiconductor storage Aug 20, 2003 Abandoned
Array ( [id] => 1057948 [patent_doc_number] => 06856558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Integrated circuit devices having high precision digital delay lines therein' [patent_app_type] => utility [patent_app_number] => 10/643208 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 13805 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856558.pdf [firstpage_image] =>[orig_patent_app_number] => 10643208 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/643208
Integrated circuit devices having high precision digital delay lines therein Aug 17, 2003 Issued
Array ( [id] => 6973780 [patent_doc_number] => 20050038952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Timing control method for operating synchronous memory' [patent_app_type] => utility [patent_app_number] => 10/640348 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4939 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20050038952.pdf [firstpage_image] =>[orig_patent_app_number] => 10640348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640348
Timing control method for operating synchronous memory Aug 11, 2003 Issued
Array ( [id] => 7626091 [patent_doc_number] => 06768675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Stack-gate flash memory array' [patent_app_type] => B1 [patent_app_number] => 10/604691 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1640 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768675.pdf [firstpage_image] =>[orig_patent_app_number] => 10604691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604691
Stack-gate flash memory array Aug 10, 2003 Issued
Array ( [id] => 7131769 [patent_doc_number] => 20040042254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor memory and method of controlling the same' [patent_app_type] => new [patent_app_number] => 10/636708 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5568 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042254.pdf [firstpage_image] =>[orig_patent_app_number] => 10636708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636708
Semiconductor memory and method of controlling the same Aug 7, 2003 Issued
Array ( [id] => 7386272 [patent_doc_number] => 20040037139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/629809 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4997 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037139.pdf [firstpage_image] =>[orig_patent_app_number] => 10629809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629809
Semiconductor memory having hierarchical bit line structure Jul 29, 2003 Issued
Array ( [id] => 7451571 [patent_doc_number] => 20040196715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'PRE-CHARGE AND SENSE-OUT CIRCUIT FOR DIFFERENTIAL TYPE ROM' [patent_app_type] => new [patent_app_number] => 10/604508 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5930 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196715.pdf [firstpage_image] =>[orig_patent_app_number] => 10604508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604508
Pre-charge and sense-out circuit for differential type ROM Jul 27, 2003 Issued
Array ( [id] => 7392564 [patent_doc_number] => 20040017706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'MRAM configuration' [patent_app_type] => new [patent_app_number] => 10/627904 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3744 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017706.pdf [firstpage_image] =>[orig_patent_app_number] => 10627904 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627904
MRAM configuration Jul 24, 2003 Issued
Array ( [id] => 1038954 [patent_doc_number] => 06873551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Apparatus and method for a configurable mirror fast sense amplifier' [patent_app_type] => utility [patent_app_number] => 10/622804 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2266 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873551.pdf [firstpage_image] =>[orig_patent_app_number] => 10622804 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622804
Apparatus and method for a configurable mirror fast sense amplifier Jul 17, 2003 Issued
Array ( [id] => 1155910 [patent_doc_number] => 06775168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Content addressable memory (CAM) devices having adjustable match line precharge circuits therein' [patent_app_type] => B1 [patent_app_number] => 10/622408 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 23052 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775168.pdf [firstpage_image] =>[orig_patent_app_number] => 10622408 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622408
Content addressable memory (CAM) devices having adjustable match line precharge circuits therein Jul 17, 2003 Issued
Array ( [id] => 7087746 [patent_doc_number] => 20050007858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method and system for reducing power when writing information to MRAM' [patent_app_type] => utility [patent_app_number] => 10/617906 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2781 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007858.pdf [firstpage_image] =>[orig_patent_app_number] => 10617906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617906
Method and system for reducing power when writing information to MRAM Jul 9, 2003 Abandoned
Array ( [id] => 1163793 [patent_doc_number] => 06765833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Integrated circuit devices including equalization/precharge circuits for improving signal transmission' [patent_app_type] => B2 [patent_app_number] => 10/617402 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6024 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765833.pdf [firstpage_image] =>[orig_patent_app_number] => 10617402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617402
Integrated circuit devices including equalization/precharge circuits for improving signal transmission Jul 9, 2003 Issued
Array ( [id] => 1023563 [patent_doc_number] => 06888733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Multiple chip system including a plurality of non-volatile semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 10/618206 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888733.pdf [firstpage_image] =>[orig_patent_app_number] => 10618206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618206
Multiple chip system including a plurality of non-volatile semiconductor memory devices Jul 8, 2003 Issued
Array ( [id] => 7087717 [patent_doc_number] => 20050007829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'SYSTEM AND METHOD FOR READING A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 10/614504 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7062 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007829.pdf [firstpage_image] =>[orig_patent_app_number] => 10614504 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614504
System and method for reading a memory cell Jul 6, 2003 Issued
Array ( [id] => 7360378 [patent_doc_number] => 20040004878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Methods of increasing write selectivity in an MRAM' [patent_app_type] => new [patent_app_number] => 10/614709 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5210 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004878.pdf [firstpage_image] =>[orig_patent_app_number] => 10614709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614709
Methods of increasing write selectivity in an MRAM Jul 6, 2003 Issued
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