Richard M. Lorence

Array ( [id] => 6859940 [patent_doc_number] => 20030090948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Semiconductor device having memory cells coupled to read and write data lines' [patent_app_type] => new [patent_app_number] => 10/325920 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11879 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20030090948.pdf [firstpage_image] =>[orig_patent_app_number] => 10325920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 670064 [patent_doc_number] => 07095647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-22 [patent_title] => 'Magnetic memory array with an improved world line configuration' [patent_app_type] => utility [patent_app_number] => 10/325008 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 14088 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095647.pdf [firstpage_image] =>[orig_patent_app_number] => 10325008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1130887 [patent_doc_number] => 06791856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Methods of increasing write selectivity in an MRAM' [patent_app_type] => B2 [patent_app_number] => 10/327581 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5151 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791856.pdf [firstpage_image] =>[orig_patent_app_number] => 10327581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7311258 [patent_doc_number] => 20040032776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Semiconductor memory device comprising circuit for precharging data line' [patent_app_type] => new [patent_app_number] => 10/324406 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3391 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20040032776.pdf [firstpage_image] =>[orig_patent_app_number] => 10324406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7463504 [patent_doc_number] => 20040120180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Variable-persistence molecular memory devices and methods of operation thereof' [patent_app_type] => new [patent_app_number] => 10/324868 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7096 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20040120180.pdf [firstpage_image] =>[orig_patent_app_number] => 10324868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7456681 [patent_doc_number] => 20040119105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Ferroelectric memory' [patent_app_type] => new [patent_app_number] => 10/325230 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10131 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119105.pdf [firstpage_image] =>[orig_patent_app_number] => 10325230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6695748 [patent_doc_number] => 20030107942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method for operating a semiconductor memory, and semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/317972 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6615 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107942.pdf [firstpage_image] =>[orig_patent_app_number] => 10317972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6681992 [patent_doc_number] => 20030117856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Memory devices with page buffer having dual registers and method of using the same' [patent_app_type] => new [patent_app_number] => 10/315897 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8118 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117856.pdf [firstpage_image] =>[orig_patent_app_number] => 10315897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 635948 [patent_doc_number] => 07130213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-31 [patent_title] => 'Methods and apparatuses for a dual-polarity non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 10/313199 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 11905 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130213.pdf [firstpage_image] =>[orig_patent_app_number] => 10313199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1145308 [patent_doc_number] => 06781890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Nonvolatile memory and processing system' [patent_app_type] => B2 [patent_app_number] => 10/308106 [patent_app_country] => US [patent_app_date] => 2002-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 17497 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781890.pdf [firstpage_image] =>[orig_patent_app_number] => 10308106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 980375 [patent_doc_number] => 06930910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Magnetic random access memory cell device using magnetic tunnel junction' [patent_app_type] => utility [patent_app_number] => 10/308174 [patent_app_country] => US [patent_app_date] => 2002-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930910.pdf [firstpage_image] =>[orig_patent_app_number] => 10308174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7401894 [patent_doc_number] => 20040105333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays' [patent_app_type] => new [patent_app_number] => 10/309572 [patent_app_country] => US [patent_app_date] => 2002-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3595 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20040105333.pdf [firstpage_image] =>[orig_patent_app_number] => 10309572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6636450 [patent_doc_number] => 20030103378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Magnetic random access memory' [patent_app_type] => new [patent_app_number] => 10/306404 [patent_app_country] => US [patent_app_date] => 2002-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7095 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20030103378.pdf [firstpage_image] =>[orig_patent_app_number] => 10306404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 791353 [patent_doc_number] => 06985379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/305004 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 12551 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985379.pdf [firstpage_image] =>[orig_patent_app_number] => 10305004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1127043 [patent_doc_number] => 06795369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Address buffer and semiconductor memory device using the same' [patent_app_type] => B2 [patent_app_number] => 10/303409 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3446 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795369.pdf [firstpage_image] =>[orig_patent_app_number] => 10303409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6682010 [patent_doc_number] => 20030117874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Semiconductor memory device capable of preventing coupling noise between adjacent bit lines in different columns' [patent_app_type] => new [patent_app_number] => 10/299407 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5346 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117874.pdf [firstpage_image] =>[orig_patent_app_number] => 10299407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1158376 [patent_doc_number] => 06771546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Semiconductor memory device and method of controlling the same' [patent_app_type] => B2 [patent_app_number] => 10/298004 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 45 [patent_no_of_words] => 18470 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771546.pdf [firstpage_image] =>[orig_patent_app_number] => 10298004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1163628 [patent_doc_number] => 06765816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Storage circuit having single-ended write circuitry' [patent_app_type] => B2 [patent_app_number] => 10/290704 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2479 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765816.pdf [firstpage_image] =>[orig_patent_app_number] => 10290704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7358191 [patent_doc_number] => 20040090817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'SPLIT LOCAL AND CONTINUOUS BITLINE REQUIRING FEWER WIRES' [patent_app_type] => new [patent_app_number] => 10/289804 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3012 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090817.pdf [firstpage_image] =>[orig_patent_app_number] => 10289804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1219902 [patent_doc_number] => 06707700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Nonovolatile ferroelectric memory device and driving method thereof' [patent_app_type] => B2 [patent_app_number] => 10/286809 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 9061 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707700.pdf [firstpage_image] =>[orig_patent_app_number] => 10286809 [rel_patent_id] =>[rel_patent_doc_number] =>)