Richard M. Lorence

Array ( [id] => 1183237 [patent_doc_number] => 06744678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Semiconductor memory device capable of masking undesired column access signal' [patent_app_type] => B2 [patent_app_number] => 10/237104 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1666 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744678.pdf [firstpage_image] =>[orig_patent_app_number] => 10237104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6859930 [patent_doc_number] => 20030090938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Nonvolatile semiconductor memory device and method of retrieving faulty in the same' [patent_app_type] => new [patent_app_number] => 10/234704 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20030090938.pdf [firstpage_image] =>[orig_patent_app_number] => 10234704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6681999 [patent_doc_number] => 20030117863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Current reducing device in sense amplifier over driver scheme of semiconductor memory chips and its method' [patent_app_type] => new [patent_app_number] => 10/234903 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4280 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117863.pdf [firstpage_image] =>[orig_patent_app_number] => 10234903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183196 [patent_doc_number] => 06744668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Flash memory array with dual function control lines and asymmetrical source and drain junctions' [patent_app_type] => B1 [patent_app_number] => 10/233906 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4803 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744668.pdf [firstpage_image] =>[orig_patent_app_number] => 10233906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6321117 [patent_doc_number] => 20020196690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/230187 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196690.pdf [firstpage_image] =>[orig_patent_app_number] => 10230187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1368017 [patent_doc_number] => 06577524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Memory structures having selectively disabled portions for power conservation' [patent_app_type] => B2 [patent_app_number] => 10/228098 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2766 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/577/06577524.pdf [firstpage_image] =>[orig_patent_app_number] => 10228098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1184594 [patent_doc_number] => 06741507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Semiconductor device outputting data at a timing with reduced jitter' [patent_app_type] => B2 [patent_app_number] => 10/224343 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6210 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741507.pdf [firstpage_image] =>[orig_patent_app_number] => 10224343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1051676 [patent_doc_number] => 06862223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT' [patent_app_type] => utility [patent_app_number] => 10/223208 [patent_app_country] => US [patent_app_date] => 2002-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 83 [patent_no_of_words] => 20366 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862223.pdf [firstpage_image] =>[orig_patent_app_number] => 10223208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1220079 [patent_doc_number] => 06707739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Two-phase pre-charge circuit and standby current erasure circuit thereof' [patent_app_type] => B2 [patent_app_number] => 10/222507 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1195 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707739.pdf [firstpage_image] =>[orig_patent_app_number] => 10222507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1164396 [patent_doc_number] => 06762959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Low-power nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/219506 [patent_app_country] => US [patent_app_date] => 2002-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4683 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762959.pdf [firstpage_image] =>[orig_patent_app_number] => 10219506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1184544 [patent_doc_number] => 06741491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Integrated dynamic memory, and method for operating the integrated dynamic memory' [patent_app_type] => B2 [patent_app_number] => 10/217907 [patent_app_country] => US [patent_app_date] => 2002-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4268 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741491.pdf [firstpage_image] =>[orig_patent_app_number] => 10217907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1163843 [patent_doc_number] => 06765838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Refresh control circuitry for refreshing storage data' [patent_app_type] => B2 [patent_app_number] => 10/209901 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 8246 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765838.pdf [firstpage_image] =>[orig_patent_app_number] => 10209901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6717397 [patent_doc_number] => 20030028745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Semiconductor storage device' [patent_app_type] => new [patent_app_number] => 10/208005 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8028 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028745.pdf [firstpage_image] =>[orig_patent_app_number] => 10208005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1045341 [patent_doc_number] => 06867989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Auto read content addressable memory cell and array' [patent_app_type] => utility [patent_app_number] => 10/207306 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8136 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867989.pdf [firstpage_image] =>[orig_patent_app_number] => 10207306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1285432 [patent_doc_number] => 06646939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Low power type Rambus DRAM' [patent_app_type] => B2 [patent_app_number] => 10/206702 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10255 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646939.pdf [firstpage_image] =>[orig_patent_app_number] => 10206702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7392639 [patent_doc_number] => 20040017719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method and apparatus for saving refresh current' [patent_app_type] => new [patent_app_number] => 10/201306 [patent_app_country] => US [patent_app_date] => 2002-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5943 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017719.pdf [firstpage_image] =>[orig_patent_app_number] => 10201306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1164389 [patent_doc_number] => 06762958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Semiconductor memory with precharge control' [patent_app_type] => B2 [patent_app_number] => 10/200902 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4530 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762958.pdf [firstpage_image] =>[orig_patent_app_number] => 10200902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7392722 [patent_doc_number] => 20040017727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Dual array read port functionality from a one port SRAM' [patent_app_type] => new [patent_app_number] => 10/201507 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2753 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017727.pdf [firstpage_image] =>[orig_patent_app_number] => 10201507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6841949 [patent_doc_number] => 20030147296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Semiconductor memory unit' [patent_app_type] => new [patent_app_number] => 10/200402 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3652 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20030147296.pdf [firstpage_image] =>[orig_patent_app_number] => 10200402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7632117 [patent_doc_number] => 06665219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method of reducing standby current during power down mode' [patent_app_type] => B2 [patent_app_number] => 10/199130 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2958 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665219.pdf [firstpage_image] =>[orig_patent_app_number] => 10199130 [rel_patent_id] =>[rel_patent_doc_number] =>)