Richard M. Lorence

Array ( [id] => 7352403 [patent_doc_number] => 20040013005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method and apparatus for reducing gate-induced diode leakage in semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/199409 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4519 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013005.pdf [firstpage_image] =>[orig_patent_app_number] => 10199409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 793870 [patent_doc_number] => 06982917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'DRAM partial refresh circuits and methods' [patent_app_type] => utility [patent_app_number] => 10/192406 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982917.pdf [firstpage_image] =>[orig_patent_app_number] => 10192406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6833631 [patent_doc_number] => 20030161176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Method for measuring bias voltage of sense amplifier in memory device' [patent_app_type] => new [patent_app_number] => 10/189506 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2808 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161176.pdf [firstpage_image] =>[orig_patent_app_number] => 10189506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1268976 [patent_doc_number] => 06661725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Apparatus for storing/restoring holographic data and method for coding/decoding holographic data' [patent_app_type] => B2 [patent_app_number] => 10/188902 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4393 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661725.pdf [firstpage_image] =>[orig_patent_app_number] => 10188902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1191093 [patent_doc_number] => 06735106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Accelerated fatigue testing' [patent_app_type] => B2 [patent_app_number] => 10/190102 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5147 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735106.pdf [firstpage_image] =>[orig_patent_app_number] => 10190102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7425837 [patent_doc_number] => 20040001376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Method and design for measuring SRAM array leakage macro (ALM)' [patent_app_type] => new [patent_app_number] => 10/064302 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2906 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001376.pdf [firstpage_image] =>[orig_patent_app_number] => 10064302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1216154 [patent_doc_number] => 06711078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Writeback and refresh circuitry for direct sensed DRAM macro' [patent_app_type] => B2 [patent_app_number] => 10/064306 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711078.pdf [firstpage_image] =>[orig_patent_app_number] => 10064306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7425854 [patent_doc_number] => 20040001378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Methods and apparatus for memory sensing' [patent_app_type] => new [patent_app_number] => 10/185206 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6545 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001378.pdf [firstpage_image] =>[orig_patent_app_number] => 10185206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1208655 [patent_doc_number] => 06717859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Automatic program- and erase-voltage generation for EEPROM cells' [patent_app_type] => B1 [patent_app_number] => 10/184709 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3551 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717859.pdf [firstpage_image] =>[orig_patent_app_number] => 10184709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824453 [patent_doc_number] => 20030235075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Vertical NROM having a storage density of 1bit per 1F2' [patent_app_type] => new [patent_app_number] => 10/177208 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9821 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235075.pdf [firstpage_image] =>[orig_patent_app_number] => 10177208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7632116 [patent_doc_number] => 06665220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Column redundancy for content addressable memory' [patent_app_type] => B2 [patent_app_number] => 10/173504 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7328 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665220.pdf [firstpage_image] =>[orig_patent_app_number] => 10173504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6667714 [patent_doc_number] => 20030112697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor device having phase error improved DLL circuit mounted thereon' [patent_app_type] => new [patent_app_number] => 10/172908 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8325 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112697.pdf [firstpage_image] =>[orig_patent_app_number] => 10172908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6656250 [patent_doc_number] => 20030009646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Circuit arrangement for the storage of digital data' [patent_app_type] => new [patent_app_number] => 10/172108 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2463 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20030009646.pdf [firstpage_image] =>[orig_patent_app_number] => 10172108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630502 [patent_doc_number] => 06636434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Multibit memory point memory' [patent_app_type] => B2 [patent_app_number] => 10/171607 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3137 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636434.pdf [firstpage_image] =>[orig_patent_app_number] => 10171607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6644203 [patent_doc_number] => 20030007407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Semiconductor memory device, method for controlling same, and electronic information apparatus' [patent_app_type] => new [patent_app_number] => 10/167806 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7492 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007407.pdf [firstpage_image] =>[orig_patent_app_number] => 10167806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1175952 [patent_doc_number] => 06754093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'CAM circuit with radiation resistance' [patent_app_type] => B2 [patent_app_number] => 10/165506 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754093.pdf [firstpage_image] =>[orig_patent_app_number] => 10165506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1069538 [patent_doc_number] => RE038685 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Data-output driver circuit and method' [patent_app_type] => reissue [patent_app_number] => 10/164354 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3967 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038685.pdf [firstpage_image] =>[orig_patent_app_number] => 10164354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6677651 [patent_doc_number] => 20030227791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems' [patent_app_type] => new [patent_app_number] => 10/163404 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5297 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227791.pdf [firstpage_image] =>[orig_patent_app_number] => 10163404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1427409 [patent_doc_number] => 06522600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Fast cycle RAM and data readout method therefor' [patent_app_type] => B2 [patent_app_number] => 10/163797 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 6946 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522600.pdf [firstpage_image] =>[orig_patent_app_number] => 10163797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1194863 [patent_doc_number] => 06731529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Variable capacitances for memory cells within a cell group' [patent_app_type] => B2 [patent_app_number] => 10/161907 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2088 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731529.pdf [firstpage_image] =>[orig_patent_app_number] => 10161907 [rel_patent_id] =>[rel_patent_doc_number] =>)