
Richard M. Lorence
Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )
| Most Active Art Unit | 3502 |
| Art Unit(s) | 3502, 3617, 3622, 0, 3655, 3656, 3681 |
| Total Applications | 3174 |
| Issued Applications | 2769 |
| Pending Applications | 79 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 704710
[patent_doc_number] => 07064987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Memory address generator with scheduled write and read address generating capability'
[patent_app_type] => utility
[patent_app_number] => 10/117029
[patent_app_country] => US
[patent_app_date] => 2002-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3131
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/064/07064987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10117029
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/117029 | Memory address generator with scheduled write and read address generating capability | Apr 3, 2002 | Issued |
Array
(
[id] => 6855120
[patent_doc_number] => 20030128621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'AUTO-DISABLE RECEIVE CONTROL FOR DDR RECEIVE STROBES'
[patent_app_type] => new
[patent_app_number] => 10/114408
[patent_app_country] => US
[patent_app_date] => 2002-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1744
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20030128621.pdf
[firstpage_image] =>[orig_patent_app_number] => 10114408
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/114408 | Auto-disable receive control for DDR receive strobes | Apr 1, 2002 | Issued |
Array
(
[id] => 1176167
[patent_doc_number] => 06754121
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-22
[patent_title] => 'Sense amplifying circuit and method'
[patent_app_type] => B2
[patent_app_number] => 10/113304
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2432
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/754/06754121.pdf
[firstpage_image] =>[orig_patent_app_number] => 10113304
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/113304 | Sense amplifying circuit and method | Mar 28, 2002 | Issued |
Array
(
[id] => 6395902
[patent_doc_number] => 20020181310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'Semiconductor memory device internal voltage generator and internal voltage generating method'
[patent_app_type] => new
[patent_app_number] => 10/112003
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2162
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20020181310.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112003
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112003 | Semiconductor memory device internal voltage generator and internal voltage generating method | Mar 27, 2002 | Issued |
Array
(
[id] => 1292149
[patent_doc_number] => 06639868
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-28
[patent_title] => 'SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals'
[patent_app_type] => B2
[patent_app_number] => 10/112108
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3459
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/639/06639868.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112108
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112108 | SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals | Mar 27, 2002 | Issued |
Array
(
[id] => 6435699
[patent_doc_number] => 20020176296
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Semiconductor memory device and redundant output switch thereof'
[patent_app_type] => new
[patent_app_number] => 10/112908
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4867
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20020176296.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112908
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112908 | Semiconductor memory device and redundant output switch thereof | Mar 26, 2002 | Issued |
Array
(
[id] => 1397839
[patent_doc_number] => 06556465
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-29
[patent_title] => 'Adjustable circuits for analog or multi-level memory'
[patent_app_type] => B2
[patent_app_number] => 10/109353
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 54
[patent_no_of_words] => 18976
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/556/06556465.pdf
[firstpage_image] =>[orig_patent_app_number] => 10109353
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/109353 | Adjustable circuits for analog or multi-level memory | Mar 26, 2002 | Issued |
Array
(
[id] => 1285426
[patent_doc_number] => 06646938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Static memory having self-timing circuit'
[patent_app_type] => B2
[patent_app_number] => 10/102703
[patent_app_country] => US
[patent_app_date] => 2002-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5763
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/646/06646938.pdf
[firstpage_image] =>[orig_patent_app_number] => 10102703
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/102703 | Static memory having self-timing circuit | Mar 21, 2002 | Issued |
Array
(
[id] => 5903595
[patent_doc_number] => 20020141247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Semiconductor device having chip selection circuit and method of generating chip selection signal'
[patent_app_type] => new
[patent_app_number] => 10/102308
[patent_app_country] => US
[patent_app_date] => 2002-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2182
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20020141247.pdf
[firstpage_image] =>[orig_patent_app_number] => 10102308
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/102308 | Semiconductor device having chip selection circuit and method of generating chip selection signal | Mar 18, 2002 | Issued |
Array
(
[id] => 1184563
[patent_doc_number] => 06741494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-25
[patent_title] => 'Magnetoelectronic memory element with inductively coupled write wires'
[patent_app_type] => B2
[patent_app_number] => 10/100210
[patent_app_country] => US
[patent_app_date] => 2002-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4627
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/741/06741494.pdf
[firstpage_image] =>[orig_patent_app_number] => 10100210
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/100210 | Magnetoelectronic memory element with inductively coupled write wires | Mar 17, 2002 | Issued |
Array
(
[id] => 1026556
[patent_doc_number] => 06885573
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-26
[patent_title] => 'Diode for use in MRAM devices and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/098206
[patent_app_country] => US
[patent_app_date] => 2002-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5446
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/885/06885573.pdf
[firstpage_image] =>[orig_patent_app_number] => 10098206
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/098206 | Diode for use in MRAM devices and method of manufacture | Mar 14, 2002 | Issued |
Array
(
[id] => 1149289
[patent_doc_number] => 06778421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-17
[patent_title] => 'Memory device array having a pair of magnetic bits sharing a common conductor line'
[patent_app_type] => B2
[patent_app_number] => 10/098903
[patent_app_country] => US
[patent_app_date] => 2002-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4015
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/778/06778421.pdf
[firstpage_image] =>[orig_patent_app_number] => 10098903
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/098903 | Memory device array having a pair of magnetic bits sharing a common conductor line | Mar 13, 2002 | Issued |
Array
(
[id] => 1291888
[patent_doc_number] => 06639827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-28
[patent_title] => 'Low standby power using shadow storage'
[patent_app_type] => B2
[patent_app_number] => 10/097202
[patent_app_country] => US
[patent_app_date] => 2002-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3280
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/639/06639827.pdf
[firstpage_image] =>[orig_patent_app_number] => 10097202
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/097202 | Low standby power using shadow storage | Mar 11, 2002 | Issued |
Array
(
[id] => 5857740
[patent_doc_number] => 20020122345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-05
[patent_title] => 'Integrated memory having a plurality of memory cell arrays'
[patent_app_type] => new
[patent_app_number] => 10/090306
[patent_app_country] => US
[patent_app_date] => 2002-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2628
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20020122345.pdf
[firstpage_image] =>[orig_patent_app_number] => 10090306
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/090306 | Integrated memory having a plurality of memory cell arrays | Mar 3, 2002 | Issued |
Array
(
[id] => 6833640
[patent_doc_number] => 20030161185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Method and system for efficiently reading and programming of dual cell memory elements'
[patent_app_type] => new
[patent_app_number] => 10/087108
[patent_app_country] => US
[patent_app_date] => 2002-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6023
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20030161185.pdf
[firstpage_image] =>[orig_patent_app_number] => 10087108
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/087108 | Method and system for efficiently reading and programming of dual cell memory elements | Feb 27, 2002 | Issued |
Array
(
[id] => 1181982
[patent_doc_number] => 06747895
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-08
[patent_title] => 'Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system'
[patent_app_type] => B2
[patent_app_number] => 10/083602
[patent_app_country] => US
[patent_app_date] => 2002-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 43
[patent_no_of_words] => 16420
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/747/06747895.pdf
[firstpage_image] =>[orig_patent_app_number] => 10083602
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/083602 | Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system | Feb 26, 2002 | Issued |
Array
(
[id] => 1322745
[patent_doc_number] => 06608782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-19
[patent_title] => 'Booster circuit capable of achieving a stable pump operation for nonvolatile semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 10/083408
[patent_app_country] => US
[patent_app_date] => 2002-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 30
[patent_no_of_words] => 8396
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/608/06608782.pdf
[firstpage_image] =>[orig_patent_app_number] => 10083408
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/083408 | Booster circuit capable of achieving a stable pump operation for nonvolatile semiconductor memory device | Feb 26, 2002 | Issued |
Array
(
[id] => 1342041
[patent_doc_number] => 06597607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-22
[patent_title] => 'Semiconductor memory device and its operation method'
[patent_app_type] => B2
[patent_app_number] => 10/074109
[patent_app_country] => US
[patent_app_date] => 2002-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 15332
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/597/06597607.pdf
[firstpage_image] =>[orig_patent_app_number] => 10074109
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/074109 | Semiconductor memory device and its operation method | Feb 11, 2002 | Issued |
Array
(
[id] => 1268907
[patent_doc_number] => 06661707
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-09
[patent_title] => 'Method of programming NAND-type flash memory'
[patent_app_type] => B2
[patent_app_number] => 10/074306
[patent_app_country] => US
[patent_app_date] => 2002-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 4573
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/661/06661707.pdf
[firstpage_image] =>[orig_patent_app_number] => 10074306
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/074306 | Method of programming NAND-type flash memory | Feb 10, 2002 | Issued |
Array
(
[id] => 1220038
[patent_doc_number] => 06707730
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-16
[patent_title] => 'Semiconductor memory device with efficient and reliable redundancy processing'
[patent_app_type] => B2
[patent_app_number] => 10/066603
[patent_app_country] => US
[patent_app_date] => 2002-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7106
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/707/06707730.pdf
[firstpage_image] =>[orig_patent_app_number] => 10066603
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/066603 | Semiconductor memory device with efficient and reliable redundancy processing | Feb 5, 2002 | Issued |