Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1268988 [patent_doc_number] => 06661728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Supply voltage generating circuit and semiconductor memory device using same' [patent_app_type] => B2 [patent_app_number] => 10/061304 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10132 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661728.pdf [firstpage_image] =>[orig_patent_app_number] => 10061304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061304
Supply voltage generating circuit and semiconductor memory device using same Feb 3, 2002 Issued
Array ( [id] => 6014025 [patent_doc_number] => 20020101756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Ferroelectric memory' [patent_app_type] => new [patent_app_number] => 10/056206 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18065 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20020101756.pdf [firstpage_image] =>[orig_patent_app_number] => 10056206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/056206
Ferroelectric memory device including a controller Jan 27, 2002 Issued
Array ( [id] => 5827166 [patent_doc_number] => 20020067636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Static semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/056069 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4689 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067636.pdf [firstpage_image] =>[orig_patent_app_number] => 10056069 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/056069
Static semiconductor memory device Jan 27, 2002 Issued
Array ( [id] => 5984026 [patent_doc_number] => 20020097609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Semiconductor storage apparatus' [patent_app_type] => new [patent_app_number] => 10/052303 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6394 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20020097609.pdf [firstpage_image] =>[orig_patent_app_number] => 10052303 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052303
Semiconductor storage apparatus Jan 17, 2002 Issued
Array ( [id] => 1470031 [patent_doc_number] => 06459627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 10/045090 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13950 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459627.pdf [firstpage_image] =>[orig_patent_app_number] => 10045090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045090
Semiconductor memory device Jan 14, 2002 Issued
Array ( [id] => 1180352 [patent_doc_number] => 06751156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Semiconductor memory system having dynamically delayed timing for high-speed data transfers' [patent_app_type] => B2 [patent_app_number] => 10/042604 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5813 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751156.pdf [firstpage_image] =>[orig_patent_app_number] => 10042604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042604
Semiconductor memory system having dynamically delayed timing for high-speed data transfers Jan 8, 2002 Issued
Array ( [id] => 1578328 [patent_doc_number] => 06469937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Current sense amplifier circuit' [patent_app_type] => B2 [patent_app_number] => 10/040788 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5865 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469937.pdf [firstpage_image] =>[orig_patent_app_number] => 10040788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040788
Current sense amplifier circuit Jan 8, 2002 Issued
Array ( [id] => 6855074 [patent_doc_number] => 20030128575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'THREE-TRANSISTOR SRAM DEVICE' [patent_app_type] => new [patent_app_number] => 10/038308 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6016 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128575.pdf [firstpage_image] =>[orig_patent_app_number] => 10038308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038308
Three-transistor SRAM device Jan 3, 2002 Issued
Array ( [id] => 6155741 [patent_doc_number] => 20020145929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Control circuit and semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/034308 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10144 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145929.pdf [firstpage_image] =>[orig_patent_app_number] => 10034308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034308
Control circuit and semiconductor memory device Jan 2, 2002 Issued
Array ( [id] => 1425908 [patent_doc_number] => 06525983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Device and method for reducing standby current in a memory device by disconnecting bit line load devices in unused columns of the memory device from a supply voltage' [patent_app_type] => B2 [patent_app_number] => 10/032643 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2047 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525983.pdf [firstpage_image] =>[orig_patent_app_number] => 10032643 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032643
Device and method for reducing standby current in a memory device by disconnecting bit line load devices in unused columns of the memory device from a supply voltage Dec 27, 2001 Issued
Array ( [id] => 6520118 [patent_doc_number] => 20020136071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for testing memory cell in semiconductor device' [patent_app_type] => new [patent_app_number] => 10/028308 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2270 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136071.pdf [firstpage_image] =>[orig_patent_app_number] => 10028308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028308
Method for testing memory cell in semiconductor device Dec 27, 2001 Issued
Array ( [id] => 6719678 [patent_doc_number] => 20030053366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Circuit for generating internal address in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/028704 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5808 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053366.pdf [firstpage_image] =>[orig_patent_app_number] => 10028704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028704
Circuit for generating internal address in semiconductor memory device Dec 27, 2001 Issued
Array ( [id] => 6371773 [patent_doc_number] => 20020118573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Method for storing data in a nonvolatile memory' [patent_app_type] => new [patent_app_number] => 10/035909 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6650 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118573.pdf [firstpage_image] =>[orig_patent_app_number] => 10035909 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035909
Method for storing data in a nonvolatile memory Dec 18, 2001 Issued
Array ( [id] => 6667713 [patent_doc_number] => 20030112696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/025100 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5884 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112696.pdf [firstpage_image] =>[orig_patent_app_number] => 10025100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025100
Semiconductor memory device Dec 17, 2001 Issued
Array ( [id] => 964953 [patent_doc_number] => 06950355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'System and method to screen defect related reliability failures in CMOS SRAMS' [patent_app_type] => utility [patent_app_number] => 10/020208 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2329 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950355.pdf [firstpage_image] =>[orig_patent_app_number] => 10020208 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020208
System and method to screen defect related reliability failures in CMOS SRAMS Dec 17, 2001 Issued
Array ( [id] => 6455010 [patent_doc_number] => 20020149963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Programming method for a multilevel memory cell' [patent_app_type] => new [patent_app_number] => 10/017502 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3940 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149963.pdf [firstpage_image] =>[orig_patent_app_number] => 10017502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017502
Programming method for a multilevel memory cell Dec 13, 2001 Issued
Array ( [id] => 991628 [patent_doc_number] => 06920075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Amplifier for reading storage cells with exclusive-OR type function' [patent_app_type] => utility [patent_app_number] => 10/450803 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3946 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920075.pdf [firstpage_image] =>[orig_patent_app_number] => 10450803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/450803
Amplifier for reading storage cells with exclusive-OR type function Dec 13, 2001 Issued
Array ( [id] => 1191150 [patent_doc_number] => 06735139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'System and method for providing asynchronous SRAM functionality with a DRAM array' [patent_app_type] => B2 [patent_app_number] => 10/017608 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4719 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735139.pdf [firstpage_image] =>[orig_patent_app_number] => 10017608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017608
System and method for providing asynchronous SRAM functionality with a DRAM array Dec 13, 2001 Issued
Array ( [id] => 1268961 [patent_doc_number] => 06661721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits' [patent_app_type] => B2 [patent_app_number] => 10/017106 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 10355 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661721.pdf [firstpage_image] =>[orig_patent_app_number] => 10017106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017106
Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits Dec 12, 2001 Issued
Array ( [id] => 1191123 [patent_doc_number] => 06735121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Nonvolatile memory system having status register for rewrite control' [patent_app_type] => B2 [patent_app_number] => 10/002010 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 9209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735121.pdf [firstpage_image] =>[orig_patent_app_number] => 10002010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002010
Nonvolatile memory system having status register for rewrite control Dec 4, 2001 Issued
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