Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5827186 [patent_doc_number] => 20020067644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver' [patent_app_type] => new [patent_app_number] => 10/001203 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2938 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067644.pdf [firstpage_image] =>[orig_patent_app_number] => 10001203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001203
Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver Dec 3, 2001 Issued
Array ( [id] => 1423437 [patent_doc_number] => 06529395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Content addressable memory cell techniques' [patent_app_type] => B1 [patent_app_number] => 10/001806 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1643 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529395.pdf [firstpage_image] =>[orig_patent_app_number] => 10001806 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001806
Content addressable memory cell techniques Nov 14, 2001 Issued
Array ( [id] => 6859913 [patent_doc_number] => 20030090921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Content addressable memory match line sensing techniques' [patent_app_type] => new [patent_app_number] => 10/002907 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1746 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20030090921.pdf [firstpage_image] =>[orig_patent_app_number] => 10002907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002907
Content addressable memory match line sensing techniques Nov 14, 2001 Abandoned
Array ( [id] => 1376989 [patent_doc_number] => 06570802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/008709 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5583 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570802.pdf [firstpage_image] =>[orig_patent_app_number] => 10008709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008709
Semiconductor memory device Nov 12, 2001 Issued
Array ( [id] => 1429241 [patent_doc_number] => 06515892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/959906 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13892 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515892.pdf [firstpage_image] =>[orig_patent_app_number] => 09959906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/959906
Semiconductor integrated circuit device Nov 12, 2001 Issued
Array ( [id] => 1249662 [patent_doc_number] => 06674686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method and apparatus for read operation and write operation in semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/037906 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4159 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674686.pdf [firstpage_image] =>[orig_patent_app_number] => 10037906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037906
Method and apparatus for read operation and write operation in semiconductor memory device Nov 8, 2001 Issued
Array ( [id] => 5934656 [patent_doc_number] => 20020060938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Semiconductor memory device and data read method thereof' [patent_app_type] => new [patent_app_number] => 10/037908 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5597 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060938.pdf [firstpage_image] =>[orig_patent_app_number] => 10037908 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037908
Semiconductor memory device and data read method thereof Nov 8, 2001 Issued
Array ( [id] => 6816841 [patent_doc_number] => 20030067799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Adjustable memory self-timing circuit' [patent_app_type] => new [patent_app_number] => 10/001702 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1690 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20030067799.pdf [firstpage_image] =>[orig_patent_app_number] => 10001702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001702
Adjustable memory self-timing circuit Oct 30, 2001 Issued
Array ( [id] => 6435568 [patent_doc_number] => 20020176286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Common source EEPROM and flash memory' [patent_app_type] => new [patent_app_number] => 10/002607 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10138 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20020176286.pdf [firstpage_image] =>[orig_patent_app_number] => 10002607 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002607
Common source EEPROM and flash memory Oct 29, 2001 Issued
Array ( [id] => 7644636 [patent_doc_number] => 06473337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Memory device having memory cells with magnetic tunnel junction and tunnel junction in series' [patent_app_type] => B1 [patent_app_number] => 09/983404 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7156 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473337.pdf [firstpage_image] =>[orig_patent_app_number] => 09983404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983404
Memory device having memory cells with magnetic tunnel junction and tunnel junction in series Oct 23, 2001 Issued
Array ( [id] => 7311254 [patent_doc_number] => 20040032772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Semiconductor memory, method for controlling refreshment of it, and method for setting memory cell array specific ara for realizing the control method' [patent_app_type] => new [patent_app_number] => 10/415604 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13576 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20040032772.pdf [firstpage_image] =>[orig_patent_app_number] => 10415604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/415604
Semiconductor memory, method for controlling refreshment of it, and method for setting memory cell array specific area for realizing the control method Oct 22, 2001 Issued
Array ( [id] => 6651969 [patent_doc_number] => 20030076732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'High performance address decode technique for arrays' [patent_app_type] => new [patent_app_number] => 10/003008 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3257 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20030076732.pdf [firstpage_image] =>[orig_patent_app_number] => 10003008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003008
High performance address decode technique for arrays Oct 22, 2001 Issued
Array ( [id] => 1396224 [patent_doc_number] => 06560148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Semiconductor memory having mirroring function' [patent_app_type] => B2 [patent_app_number] => 09/978006 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 10985 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560148.pdf [firstpage_image] =>[orig_patent_app_number] => 09978006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978006
Semiconductor memory having mirroring function Oct 16, 2001 Issued
Array ( [id] => 6287914 [patent_doc_number] => 20020054523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Activation of word lines in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/976108 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13157 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20020054523.pdf [firstpage_image] =>[orig_patent_app_number] => 09976108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976108
Activation of word lines in semiconductor memory device Oct 14, 2001 Issued
Array ( [id] => 1319318 [patent_doc_number] => 06614706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Voltage regulating circuit, in particular for semiconductor memories' [patent_app_type] => B2 [patent_app_number] => 09/977805 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2498 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614706.pdf [firstpage_image] =>[orig_patent_app_number] => 09977805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977805
Voltage regulating circuit, in particular for semiconductor memories Oct 14, 2001 Issued
Array ( [id] => 1520453 [patent_doc_number] => 06501697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'High density memory sense amplifier' [patent_app_type] => B1 [patent_app_number] => 09/976304 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501697.pdf [firstpage_image] =>[orig_patent_app_number] => 09976304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976304
High density memory sense amplifier Oct 10, 2001 Issued
Array ( [id] => 1429487 [patent_doc_number] => 06515920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor data storing circuit device, method of checking the device and method of relieving the device from defective cell' [patent_app_type] => B2 [patent_app_number] => 09/970708 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 20763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515920.pdf [firstpage_image] =>[orig_patent_app_number] => 09970708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/970708
Semiconductor data storing circuit device, method of checking the device and method of relieving the device from defective cell Oct 4, 2001 Issued
Array ( [id] => 1241993 [patent_doc_number] => 06683816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Access control system for multi-banked DRAM memory' [patent_app_type] => B2 [patent_app_number] => 09/972408 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3836 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683816.pdf [firstpage_image] =>[orig_patent_app_number] => 09972408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972408
Access control system for multi-banked DRAM memory Oct 4, 2001 Issued
Array ( [id] => 1288219 [patent_doc_number] => 06643180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Semiconductor memory device with test mode' [patent_app_type] => B2 [patent_app_number] => 09/968706 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 15361 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643180.pdf [firstpage_image] =>[orig_patent_app_number] => 09968706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968706
Semiconductor memory device with test mode Oct 1, 2001 Issued
Array ( [id] => 1572629 [patent_doc_number] => 06498739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Applications for non-volatile memory cells' [patent_app_type] => B2 [patent_app_number] => 09/968643 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5918 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498739.pdf [firstpage_image] =>[orig_patent_app_number] => 09968643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968643
Applications for non-volatile memory cells Sep 30, 2001 Issued
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