Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7644647 [patent_doc_number] => 06473326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Memory structures having selectively disabled portions for power conservation' [patent_app_type] => B2 [patent_app_number] => 09/884055 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2740 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473326.pdf [firstpage_image] =>[orig_patent_app_number] => 09884055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884055
Memory structures having selectively disabled portions for power conservation Jun 19, 2001 Issued
Array ( [id] => 1454373 [patent_doc_number] => 06456536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of programming a non-volatile memory cell using a substrate bias' [patent_app_type] => B1 [patent_app_number] => 09/884409 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9176 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456536.pdf [firstpage_image] =>[orig_patent_app_number] => 09884409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884409
Method of programming a non-volatile memory cell using a substrate bias Jun 18, 2001 Issued
Array ( [id] => 1454345 [patent_doc_number] => 06456531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of drain avalanche programming of a non-volatile memory cell' [patent_app_type] => B1 [patent_app_number] => 09/884402 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9077 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456531.pdf [firstpage_image] =>[orig_patent_app_number] => 09884402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884402
Method of drain avalanche programming of a non-volatile memory cell Jun 18, 2001 Issued
Array ( [id] => 7644648 [patent_doc_number] => 06473325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Bit line sensing control circuit for a semiconductor memory device and layout of the same' [patent_app_type] => B2 [patent_app_number] => 09/882209 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3958 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473325.pdf [firstpage_image] =>[orig_patent_app_number] => 09882209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882209
Bit line sensing control circuit for a semiconductor memory device and layout of the same Jun 14, 2001 Issued
Array ( [id] => 1600147 [patent_doc_number] => 06493278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Semiconductor device and control device for use therewith' [patent_app_type] => B2 [patent_app_number] => 09/882602 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11495 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493278.pdf [firstpage_image] =>[orig_patent_app_number] => 09882602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882602
Semiconductor device and control device for use therewith Jun 14, 2001 Issued
Array ( [id] => 1473297 [patent_doc_number] => 06407947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method of erasing a flash memory device' [patent_app_type] => B2 [patent_app_number] => 09/882106 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2768 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407947.pdf [firstpage_image] =>[orig_patent_app_number] => 09882106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882106
Method of erasing a flash memory device Jun 14, 2001 Issued
Array ( [id] => 6879610 [patent_doc_number] => 20010030896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/877039 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 22158 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20010030896.pdf [firstpage_image] =>[orig_patent_app_number] => 09877039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/877039
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPLEMENTING REDUNDANCY-BASED REPAIR EFFICIENTLY IN RELATION TO LAYOUT AND OPERATING SPEED AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING SUCH SEMICONDUCTOR MEMORY DEVICE Jun 10, 2001 Issued
Array ( [id] => 1564324 [patent_doc_number] => 06438059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Fuse programming circuit for programming fuses' [patent_app_type] => B2 [patent_app_number] => 09/874208 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5733 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438059.pdf [firstpage_image] =>[orig_patent_app_number] => 09874208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874208
Fuse programming circuit for programming fuses Jun 5, 2001 Issued
Array ( [id] => 6986271 [patent_doc_number] => 20010036103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Solid-state memory with magnetic storage cells' [patent_app_type] => new [patent_app_number] => 09/871386 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3638 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036103.pdf [firstpage_image] =>[orig_patent_app_number] => 09871386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871386
Solid-state memory with magnetic storage cells May 30, 2001 Abandoned
Array ( [id] => 1431654 [patent_doc_number] => 06504746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'High-density low-cost read-only memory circuit' [patent_app_type] => B2 [patent_app_number] => 09/871504 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1598 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504746.pdf [firstpage_image] =>[orig_patent_app_number] => 09871504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871504
High-density low-cost read-only memory circuit May 30, 2001 Issued
Array ( [id] => 6882154 [patent_doc_number] => 20010048626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Virtual channel DRAM' [patent_app_type] => new [patent_app_number] => 09/864202 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4587 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048626.pdf [firstpage_image] =>[orig_patent_app_number] => 09864202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864202
Channel driving circuit of virtual channel DRAM May 24, 2001 Issued
Array ( [id] => 6999311 [patent_doc_number] => 20010053092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Memory system and programming method thereof' [patent_app_type] => new [patent_app_number] => 09/864406 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10755 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053092.pdf [firstpage_image] =>[orig_patent_app_number] => 09864406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864406
Memory system and programming method thereof May 24, 2001 Issued
Array ( [id] => 7374575 [patent_doc_number] => 20040027849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Organic bistable device and organic memory cells' [patent_app_type] => new [patent_app_number] => 10/399586 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5916 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027849.pdf [firstpage_image] =>[orig_patent_app_number] => 10399586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/399586
Organic bistable device and organic memory cells May 23, 2001 Issued
Array ( [id] => 7639174 [patent_doc_number] => 06396743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Control circuit for a non-volatile memory array for controlling the ramp rate of high voltage applied to the memory cells and to limit the current drawn therefrom' [patent_app_type] => B1 [patent_app_number] => 09/860706 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2049 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396743.pdf [firstpage_image] =>[orig_patent_app_number] => 09860706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860706
Control circuit for a non-volatile memory array for controlling the ramp rate of high voltage applied to the memory cells and to limit the current drawn therefrom May 17, 2001 Issued
Array ( [id] => 7644649 [patent_doc_number] => 06473324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Layout of a sense amplifier with accelerated signal evaluation' [patent_app_type] => B2 [patent_app_number] => 09/849908 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3877 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473324.pdf [firstpage_image] =>[orig_patent_app_number] => 09849908 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849908
Layout of a sense amplifier with accelerated signal evaluation May 3, 2001 Issued
Array ( [id] => 1552229 [patent_doc_number] => 06347048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/841105 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9257 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347048.pdf [firstpage_image] =>[orig_patent_app_number] => 09841105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841105
Semiconductor memory device Apr 24, 2001 Issued
Array ( [id] => 6985543 [patent_doc_number] => 20010035536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Integrated semiconductor circuit, in particular a semiconductor memory configuration, and method for its operation' [patent_app_type] => new [patent_app_number] => 09/833008 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2685 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035536.pdf [firstpage_image] =>[orig_patent_app_number] => 09833008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/833008
Integrated semiconductor circuit, in particular a semiconductor memory configuration, and method for its operation Apr 10, 2001 Issued
Array ( [id] => 1457750 [patent_doc_number] => 06462980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'MRAM memory with drive logic arrangement' [patent_app_type] => B2 [patent_app_number] => 09/832106 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462980.pdf [firstpage_image] =>[orig_patent_app_number] => 09832106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832106
MRAM memory with drive logic arrangement Apr 10, 2001 Issued
Array ( [id] => 1564174 [patent_doc_number] => 06438015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Semiconductor memory device and memory system for improving bus efficiency' [patent_app_type] => B1 [patent_app_number] => 09/829803 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3439 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438015.pdf [firstpage_image] =>[orig_patent_app_number] => 09829803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829803
Semiconductor memory device and memory system for improving bus efficiency Apr 9, 2001 Issued
Array ( [id] => 5948549 [patent_doc_number] => 20020005547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Semiconductor memory apparatus and method for outputting data' [patent_app_type] => new [patent_app_number] => 09/835609 [patent_app_country] => US [patent_app_date] => 2001-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20020005547.pdf [firstpage_image] =>[orig_patent_app_number] => 09835609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835609
Semiconductor memory apparatus and method for outputting data Apr 9, 2001 Issued
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