Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1585295 [patent_doc_number] => 06424558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-23 [patent_title] => 'Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines' [patent_app_type] => B2 [patent_app_number] => 09/767804 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4256 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424558.pdf [firstpage_image] =>[orig_patent_app_number] => 09767804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767804
Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines Jan 21, 2001 Issued
Array ( [id] => 1555070 [patent_doc_number] => 06400604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Nonvolatile semiconductor memory device having a data reprogram mode' [patent_app_type] => B2 [patent_app_number] => 09/764108 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6849 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400604.pdf [firstpage_image] =>[orig_patent_app_number] => 09764108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764108
Nonvolatile semiconductor memory device having a data reprogram mode Jan 18, 2001 Issued
Array ( [id] => 1555053 [patent_doc_number] => 06400597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/760802 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3665 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400597.pdf [firstpage_image] =>[orig_patent_app_number] => 09760802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760802
Semiconductor memory device Jan 16, 2001 Issued
Array ( [id] => 1502288 [patent_doc_number] => 06486519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor memory device with reduce coupling capacitance' [patent_app_type] => B2 [patent_app_number] => 09/758806 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6157 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486519.pdf [firstpage_image] =>[orig_patent_app_number] => 09758806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758806
Semiconductor memory device with reduce coupling capacitance Jan 15, 2001 Issued
Array ( [id] => 1523381 [patent_doc_number] => 06414898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method to reduce peak current for RAS cycle sensing in DRAM using non-multiplexed row and column addresses to avoid damage to battery' [patent_app_type] => B1 [patent_app_number] => 09/759907 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414898.pdf [firstpage_image] =>[orig_patent_app_number] => 09759907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759907
Method to reduce peak current for RAS cycle sensing in DRAM using non-multiplexed row and column addresses to avoid damage to battery Jan 15, 2001 Issued
Array ( [id] => 1493321 [patent_doc_number] => 06418047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'System and method for storing data in read-only memory' [patent_app_type] => B1 [patent_app_number] => 09/757108 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5097 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418047.pdf [firstpage_image] =>[orig_patent_app_number] => 09757108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757108
System and method for storing data in read-only memory Jan 7, 2001 Issued
Array ( [id] => 6596366 [patent_doc_number] => 20020085404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Smart random access memory' [patent_app_type] => new [patent_app_number] => 09/753604 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1121 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085404.pdf [firstpage_image] =>[orig_patent_app_number] => 09753604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753604
Smart random access memory Jan 3, 2001 Abandoned
Array ( [id] => 6902082 [patent_doc_number] => 20010000991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new-utility [patent_app_number] => 09/750038 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13983 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000991.pdf [firstpage_image] =>[orig_patent_app_number] => 09750038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750038
Dynamic random access memory in switch MOSFETs between sense amplifiers and bit lines Dec 28, 2000 Issued
Array ( [id] => 6596453 [patent_doc_number] => 20020085407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'CIRCUIT AND METHOD FOR ASYNCHRONOUSLY ACCESSING A FERROELECTRIC MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 09/752209 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4040 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085407.pdf [firstpage_image] =>[orig_patent_app_number] => 09752209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752209
Circuit and method for asynchronously accessing a ferroelectric memory device Dec 28, 2000 Issued
Array ( [id] => 6876330 [patent_doc_number] => 20010006483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Fast cycle RAM and data readout method therefor' [patent_app_type] => new-utility [patent_app_number] => 09/749008 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7998 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006483.pdf [firstpage_image] =>[orig_patent_app_number] => 09749008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749008
Fast cycle RAM and data readout method therefor Dec 26, 2000 Issued
Array ( [id] => 1482891 [patent_doc_number] => 06452837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-17 [patent_title] => 'Nonvolatile semiconductor memory and threshold voltage control method therefor' [patent_app_type] => B2 [patent_app_number] => 09/745802 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 61 [patent_no_of_words] => 22450 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452837.pdf [firstpage_image] =>[orig_patent_app_number] => 09745802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745802
Nonvolatile semiconductor memory and threshold voltage control method therefor Dec 25, 2000 Issued
Array ( [id] => 1389876 [patent_doc_number] => 06563739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'System and method for transferring data between different types of memory using a common data bus' [patent_app_type] => B2 [patent_app_number] => 09/740802 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563739.pdf [firstpage_image] =>[orig_patent_app_number] => 09740802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740802
System and method for transferring data between different types of memory using a common data bus Dec 20, 2000 Issued
Array ( [id] => 6466601 [patent_doc_number] => 20020021591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Plural line buffer type memory LSI' [patent_app_type] => new [patent_app_number] => 09/746809 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6467 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021591.pdf [firstpage_image] =>[orig_patent_app_number] => 09746809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746809
Plural line buffer type memory LSI Dec 19, 2000 Issued
Array ( [id] => 1409908 [patent_doc_number] => 06545892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout' [patent_app_type] => B2 [patent_app_number] => 09/741304 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8938 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545892.pdf [firstpage_image] =>[orig_patent_app_number] => 09741304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741304
Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout Dec 18, 2000 Issued
Array ( [id] => 1523357 [patent_doc_number] => 06414885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor integrated circuit and integrated circuit system' [patent_app_type] => B1 [patent_app_number] => 09/739402 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 14720 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414885.pdf [firstpage_image] =>[orig_patent_app_number] => 09739402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739402
Semiconductor integrated circuit and integrated circuit system Dec 18, 2000 Issued
Array ( [id] => 1482916 [patent_doc_number] => 06452843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method and apparatus for testing high-speed circuits based on slow-speed signals' [patent_app_type] => B1 [patent_app_number] => 09/740702 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5341 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452843.pdf [firstpage_image] =>[orig_patent_app_number] => 09740702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740702
Method and apparatus for testing high-speed circuits based on slow-speed signals Dec 18, 2000 Issued
Array ( [id] => 1473296 [patent_doc_number] => 06407946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/731005 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2806 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407946.pdf [firstpage_image] =>[orig_patent_app_number] => 09731005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731005
Nonvolatile semiconductor memory device Dec 6, 2000 Issued
Array ( [id] => 1531201 [patent_doc_number] => 06480433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Dynamic random access memory with differential signal on-chip test capability' [patent_app_type] => B2 [patent_app_number] => 09/727604 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1899 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480433.pdf [firstpage_image] =>[orig_patent_app_number] => 09727604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727604
Dynamic random access memory with differential signal on-chip test capability Nov 30, 2000 Issued
Array ( [id] => 1555052 [patent_doc_number] => 06400596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Semiconductor memory device using open data line arrangement' [patent_app_type] => B2 [patent_app_number] => 09/725107 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 9536 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400596.pdf [firstpage_image] =>[orig_patent_app_number] => 09725107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725107
Semiconductor memory device using open data line arrangement Nov 28, 2000 Issued
Array ( [id] => 1437687 [patent_doc_number] => 06356488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Bias level generating circuit in a flash memory device' [patent_app_type] => B1 [patent_app_number] => 09/722107 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3273 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356488.pdf [firstpage_image] =>[orig_patent_app_number] => 09722107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722107
Bias level generating circuit in a flash memory device Nov 26, 2000 Issued
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