Richard M. Lorence

Array ( [id] => 1552296 [patent_doc_number] => 06347060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Hologram observation method and hologram observation apparatus and multi-dimensional hologram data processing method and multi-dimensional hologram data processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/675506 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7872 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347060.pdf [firstpage_image] =>[orig_patent_app_number] => 09675506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416240 [patent_doc_number] => 06272040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'System and method for programming a magnetoresistive memory device' [patent_app_type] => 1 [patent_app_number] => 9/675204 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 22728 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272040.pdf [firstpage_image] =>[orig_patent_app_number] => 675204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317973 [patent_doc_number] => 06252795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Programmable resistive circuit using magnetoresistive memory technology' [patent_app_type] => 1 [patent_app_number] => 9/675203 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 22700 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252795.pdf [firstpage_image] =>[orig_patent_app_number] => 675203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4344617 [patent_doc_number] => 06314020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Analog functional module using magnetoresistive memory technology' [patent_app_type] => 1 [patent_app_number] => 9/675202 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 22828 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314020.pdf [firstpage_image] =>[orig_patent_app_number] => 675202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1599605 [patent_doc_number] => 06385073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Integrated circuit device with expandable nonvolatile memory' [patent_app_type] => B1 [patent_app_number] => 09/675106 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2440 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385073.pdf [firstpage_image] =>[orig_patent_app_number] => 09675106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4329665 [patent_doc_number] => 06331955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/662102 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2589 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331955.pdf [firstpage_image] =>[orig_patent_app_number] => 662102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1450044 [patent_doc_number] => 06370071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'High voltage CMOS switch' [patent_app_type] => B1 [patent_app_number] => 09/660707 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4514 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370071.pdf [firstpage_image] =>[orig_patent_app_number] => 09660707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416470 [patent_doc_number] => 06272064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Memory with combined synchronous burst and bus efficient functionality' [patent_app_type] => 1 [patent_app_number] => 9/652775 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5083 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272064.pdf [firstpage_image] =>[orig_patent_app_number] => 652775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1564190 [patent_doc_number] => 06438020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Ferroelectric memory device having an internal supply voltage, which is lower than the external supply voltage, supplied to the memory cells' [patent_app_type] => B1 [patent_app_number] => 09/651104 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5352 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438020.pdf [firstpage_image] =>[orig_patent_app_number] => 09651104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1517636 [patent_doc_number] => 06421266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Memory circuit having improved sense-amplifier block and method for forming same' [patent_app_type] => B1 [patent_app_number] => 09/649344 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5726 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421266.pdf [firstpage_image] =>[orig_patent_app_number] => 09649344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1442638 [patent_doc_number] => 06496434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Differential sensing in a memory using two cycle pre-charge' [patent_app_type] => B1 [patent_app_number] => 09/648706 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7174 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496434.pdf [firstpage_image] =>[orig_patent_app_number] => 09648706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4339411 [patent_doc_number] => 06330197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'System for linearizing a programmable delay circuit' [patent_app_type] => 1 [patent_app_number] => 9/628702 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4111 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330197.pdf [firstpage_image] =>[orig_patent_app_number] => 628702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419381 [patent_doc_number] => 06301175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Memory device with single-ended sensing and low voltage pre-charge' [patent_app_type] => 1 [patent_app_number] => 9/626215 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 32 [patent_no_of_words] => 5630 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301175.pdf [firstpage_image] =>[orig_patent_app_number] => 626215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 983575 [patent_doc_number] => 06928025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'Synchronous integrated memory' [patent_app_type] => utility [patent_app_number] => 09/621905 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2587 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928025.pdf [firstpage_image] =>[orig_patent_app_number] => 09621905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1442562 [patent_doc_number] => 06496409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Variable capacity semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/620719 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4863 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496409.pdf [firstpage_image] =>[orig_patent_app_number] => 09620719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585307 [patent_doc_number] => 06424561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'MRAM architecture using offset bits for increased write selectivity' [patent_app_type] => B1 [patent_app_number] => 09/618504 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5012 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424561.pdf [firstpage_image] =>[orig_patent_app_number] => 09618504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1546864 [patent_doc_number] => 06373754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor memory device having stable internal supply voltage driver' [patent_app_type] => B1 [patent_app_number] => 09/617208 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3025 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373754.pdf [firstpage_image] =>[orig_patent_app_number] => 09617208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416958 [patent_doc_number] => 06233188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Precharge control signal generating circuit' [patent_app_type] => 1 [patent_app_number] => 9/617121 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7917 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233188.pdf [firstpage_image] =>[orig_patent_app_number] => 617121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1536873 [patent_doc_number] => 06411548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Semiconductor memory having transistors connected in series' [patent_app_type] => B1 [patent_app_number] => 09/615803 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 72 [patent_no_of_words] => 46093 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411548.pdf [firstpage_image] =>[orig_patent_app_number] => 09615803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1520403 [patent_doc_number] => 06501670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'High speed memory architecture and busing' [patent_app_type] => B1 [patent_app_number] => 09/607802 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3595 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501670.pdf [firstpage_image] =>[orig_patent_app_number] => 09607802 [rel_patent_id] =>[rel_patent_doc_number] =>)