Richard M. Lorence

Array ( [id] => 4345038 [patent_doc_number] => 06314046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Dual memory control circuit' [patent_app_type] => 1 [patent_app_number] => 9/535604 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3507 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314046.pdf [firstpage_image] =>[orig_patent_app_number] => 535604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507420 [patent_doc_number] => 06466502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Semiconductor memory device having switching and memory cell transistors with the memory cell having the lower threshold voltage' [patent_app_type] => B1 [patent_app_number] => 09/537804 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 10880 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466502.pdf [firstpage_image] =>[orig_patent_app_number] => 09537804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478433 [patent_doc_number] => 06388916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Magnetoelectronic memory element with isolation element' [patent_app_type] => B1 [patent_app_number] => 09/532706 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4605 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388916.pdf [firstpage_image] =>[orig_patent_app_number] => 09532706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1538484 [patent_doc_number] => 06337826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Clock synchronization semiconductor memory device sequentially outputting data bit by bit' [patent_app_type] => B1 [patent_app_number] => 09/527306 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 85 [patent_no_of_words] => 11693 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337826.pdf [firstpage_image] =>[orig_patent_app_number] => 09527306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381149 [patent_doc_number] => 06275438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Circuit for applying power to static random access memory cell' [patent_app_type] => 1 [patent_app_number] => 9/525908 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275438.pdf [firstpage_image] =>[orig_patent_app_number] => 525908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317825 [patent_doc_number] => 06327190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Complementary differential input buffer for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/521904 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3212 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327190.pdf [firstpage_image] =>[orig_patent_app_number] => 521904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298780 [patent_doc_number] => 06269048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor memory device for inputting/outputting data through a common terminal and outputting data in synchronism with clock' [patent_app_type] => 1 [patent_app_number] => 9/515508 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4210 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269048.pdf [firstpage_image] =>[orig_patent_app_number] => 515508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4393190 [patent_doc_number] => 06304487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Register driven means to control programming voltages' [patent_app_type] => 1 [patent_app_number] => 9/514404 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7378 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304487.pdf [firstpage_image] =>[orig_patent_app_number] => 514404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1443030 [patent_doc_number] => 06335891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Device and method for reducing standby current in a memory device by disconnecting bit line load devices in unused columns of the memory device from a supply voltage' [patent_app_type] => B1 [patent_app_number] => 09/513805 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335891.pdf [firstpage_image] =>[orig_patent_app_number] => 09513805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407069 [patent_doc_number] => 06297988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Mode indicator for multi-level memory' [patent_app_type] => 1 [patent_app_number] => 9/513402 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297988.pdf [firstpage_image] =>[orig_patent_app_number] => 513402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302850 [patent_doc_number] => 06212126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor device including clock generation circuit capable of generating internal clock stably' [patent_app_type] => 1 [patent_app_number] => 9/512106 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 1 [patent_no_of_words] => 8231 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212126.pdf [firstpage_image] =>[orig_patent_app_number] => 512106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326484 [patent_doc_number] => 06317379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Determine output of a read/write port' [patent_app_type] => 1 [patent_app_number] => 9/507506 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317379.pdf [firstpage_image] =>[orig_patent_app_number] => 507506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309240 [patent_doc_number] => 06198671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/506102 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 17314 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198671.pdf [firstpage_image] =>[orig_patent_app_number] => 506102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309449 [patent_doc_number] => 06181630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of stabilizing data stored in volatile memory' [patent_app_type] => 1 [patent_app_number] => 9/499702 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1239 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181630.pdf [firstpage_image] =>[orig_patent_app_number] => 499702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4358617 [patent_doc_number] => 06285578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Hidden refresh pseudo SRAM and hidden refresh method' [patent_app_type] => 1 [patent_app_number] => 9/477906 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285578.pdf [firstpage_image] =>[orig_patent_app_number] => 477906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363720 [patent_doc_number] => 06215711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Row address strobe signal generating device' [patent_app_type] => 1 [patent_app_number] => 9/475306 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2110 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215711.pdf [firstpage_image] =>[orig_patent_app_number] => 475306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407263 [patent_doc_number] => 06298006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method and apparatus to automatically determine the size of an external EEPROM' [patent_app_type] => 1 [patent_app_number] => 9/476302 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298006.pdf [firstpage_image] =>[orig_patent_app_number] => 476302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302608 [patent_doc_number] => 06212110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/471504 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212110.pdf [firstpage_image] =>[orig_patent_app_number] => 471504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416201 [patent_doc_number] => 06272036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage' [patent_app_type] => 1 [patent_app_number] => 9/467808 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3967 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272036.pdf [firstpage_image] =>[orig_patent_app_number] => 467808 [rel_patent_id] =>[rel_patent_doc_number] =>)