
Richard M. Lorence
Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )
| Most Active Art Unit | 3502 |
| Art Unit(s) | 3502, 3617, 3622, 0, 3655, 3656, 3681 |
| Total Applications | 3174 |
| Issued Applications | 2769 |
| Pending Applications | 79 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 09/255497 | TERNARY CONTENT ADDRESSABLE MEMORY CELL | Feb 22, 1999 | Abandoned |
Array
(
[id] => 4197519
[patent_doc_number] => 06151238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Calibrating functions of an integrated circuit and storing calibration parameters thereof in a programmable fuse array'
[patent_app_type] => 1
[patent_app_number] => 9/256598
[patent_app_country] => US
[patent_app_date] => 1999-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3340
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/151/06151238.pdf
[firstpage_image] =>[orig_patent_app_number] => 256598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/256598 | Calibrating functions of an integrated circuit and storing calibration parameters thereof in a programmable fuse array | Feb 22, 1999 | Issued |
Array
(
[id] => 4197429
[patent_doc_number] => 06094395
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMs'
[patent_app_type] => 1
[patent_app_number] => 9/253996
[patent_app_country] => US
[patent_app_date] => 1999-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6367
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094395.pdf
[firstpage_image] =>[orig_patent_app_number] => 253996
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/253996 | Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMs | Feb 21, 1999 | Issued |
Array
(
[id] => 4170141
[patent_doc_number] => 06157563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Ferroelectric memory system and method of driving the same'
[patent_app_type] => 1
[patent_app_number] => 9/147598
[patent_app_country] => US
[patent_app_date] => 1999-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 26
[patent_no_of_words] => 11702
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/157/06157563.pdf
[firstpage_image] =>[orig_patent_app_number] => 147598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/147598 | Ferroelectric memory system and method of driving the same | Jan 28, 1999 | Issued |
Array
(
[id] => 1480144
[patent_doc_number] => 06345012
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Tri-stating address input circuit'
[patent_app_type] => B1
[patent_app_number] => 09/233299
[patent_app_country] => US
[patent_app_date] => 1999-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2217
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/345/06345012.pdf
[firstpage_image] =>[orig_patent_app_number] => 09233299
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/233299 | Tri-stating address input circuit | Jan 18, 1999 | Issued |
Array
(
[id] => 4216928
[patent_doc_number] => 06078531
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Word line voltage supply circuit'
[patent_app_type] => 1
[patent_app_number] => 9/232696
[patent_app_country] => US
[patent_app_date] => 1999-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 35
[patent_no_of_words] => 8008
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078531.pdf
[firstpage_image] =>[orig_patent_app_number] => 232696
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/232696 | Word line voltage supply circuit | Jan 18, 1999 | Issued |
Array
(
[id] => 4426392
[patent_doc_number] => 06226202
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'Flash memory card including CIS information'
[patent_app_type] => 1
[patent_app_number] => 9/233099
[patent_app_country] => US
[patent_app_date] => 1999-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 7816
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/226/06226202.pdf
[firstpage_image] =>[orig_patent_app_number] => 233099
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/233099 | Flash memory card including CIS information | Jan 18, 1999 | Issued |
Array
(
[id] => 6893550
[patent_doc_number] => 20010015916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'STORAGE CELLS UTILIZING REDUCED PASS GATE VOLTAGES FOR READ AND WRITE OPERATIONS'
[patent_app_type] => new
[patent_app_number] => 09/231998
[patent_app_country] => US
[patent_app_date] => 1999-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8633
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20010015916.pdf
[firstpage_image] =>[orig_patent_app_number] => 09231998
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/231998 | STORAGE CELLS UTILIZING REDUCED PASS GATE VOLTAGES FOR READ AND WRITE OPERATIONS | Jan 14, 1999 | Abandoned |
Array
(
[id] => 4159860
[patent_doc_number] => 06064627
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Synchronous semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/231397
[patent_app_country] => US
[patent_app_date] => 1999-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1898
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/064/06064627.pdf
[firstpage_image] =>[orig_patent_app_number] => 231397
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/231397 | Synchronous semiconductor memory device | Jan 11, 1999 | Issued |
Array
(
[id] => 4317226
[patent_doc_number] => 06188632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Dual access memory array'
[patent_app_type] => 1
[patent_app_number] => 9/226397
[patent_app_country] => US
[patent_app_date] => 1999-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5525
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/188/06188632.pdf
[firstpage_image] =>[orig_patent_app_number] => 226397
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/226397 | Dual access memory array | Jan 5, 1999 | Issued |
Array
(
[id] => 4197778
[patent_doc_number] => 06151254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Non-volatile semiconductor memory device and data erase method of non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/222496
[patent_app_country] => US
[patent_app_date] => 1998-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 5376
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/151/06151254.pdf
[firstpage_image] =>[orig_patent_app_number] => 222496
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222496 | Non-volatile semiconductor memory device and data erase method of non-volatile semiconductor memory device | Dec 27, 1998 | Issued |
Array
(
[id] => 4169820
[patent_doc_number] => 06108235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Memory device'
[patent_app_type] => 1
[patent_app_number] => 9/217197
[patent_app_country] => US
[patent_app_date] => 1998-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5503
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108235.pdf
[firstpage_image] =>[orig_patent_app_number] => 217197
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/217197 | Memory device | Dec 21, 1998 | Issued |
Array
(
[id] => 4191758
[patent_doc_number] => 06038161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Ferroelectric memory'
[patent_app_type] => 1
[patent_app_number] => 9/209096
[patent_app_country] => US
[patent_app_date] => 1998-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3593
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/038/06038161.pdf
[firstpage_image] =>[orig_patent_app_number] => 209096
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/209096 | Ferroelectric memory | Dec 9, 1998 | Issued |
Array
(
[id] => 4096312
[patent_doc_number] => 06018483
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Distributed block redundancy for memory devices'
[patent_app_type] => 1
[patent_app_number] => 9/209199
[patent_app_country] => US
[patent_app_date] => 1998-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2275
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018483.pdf
[firstpage_image] =>[orig_patent_app_number] => 209199
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/209199 | Distributed block redundancy for memory devices | Dec 9, 1998 | Issued |
Array
(
[id] => 4145262
[patent_doc_number] => 06147903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Non-volatile semiconductor memory device and method for driving the same'
[patent_app_type] => 1
[patent_app_number] => 9/207297
[patent_app_country] => US
[patent_app_date] => 1998-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8726
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/147/06147903.pdf
[firstpage_image] =>[orig_patent_app_number] => 207297
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207297 | Non-volatile semiconductor memory device and method for driving the same | Dec 7, 1998 | Issued |
Array
(
[id] => 4216831
[patent_doc_number] => 06078524
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'High speed sensing circuit for a memory device'
[patent_app_type] => 1
[patent_app_number] => 9/206362
[patent_app_country] => US
[patent_app_date] => 1998-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4322
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078524.pdf
[firstpage_image] =>[orig_patent_app_number] => 206362
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206362 | High speed sensing circuit for a memory device | Dec 6, 1998 | Issued |
Array
(
[id] => 4126728
[patent_doc_number] => 06046933
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Nonvolatile semiconductor memory device and IC memory card using same'
[patent_app_type] => 1
[patent_app_number] => 9/203597
[patent_app_country] => US
[patent_app_date] => 1998-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 62
[patent_no_of_words] => 11051
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/046/06046933.pdf
[firstpage_image] =>[orig_patent_app_number] => 203597
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/203597 | Nonvolatile semiconductor memory device and IC memory card using same | Dec 1, 1998 | Issued |
Array
(
[id] => 4197918
[patent_doc_number] => 06151263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Integrated circuit memory devices having data input and output lines extending along the column direction'
[patent_app_type] => 1
[patent_app_number] => 9/203262
[patent_app_country] => US
[patent_app_date] => 1998-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6083
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/151/06151263.pdf
[firstpage_image] =>[orig_patent_app_number] => 203262
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/203262 | Integrated circuit memory devices having data input and output lines extending along the column direction | Nov 30, 1998 | Issued |
Array
(
[id] => 4144359
[patent_doc_number] => 06034895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Method and circuit for the programming and erasure of a memory'
[patent_app_type] => 1
[patent_app_number] => 9/198431
[patent_app_country] => US
[patent_app_date] => 1998-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4731
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/034/06034895.pdf
[firstpage_image] =>[orig_patent_app_number] => 198431
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/198431 | Method and circuit for the programming and erasure of a memory | Nov 23, 1998 | Issued |
Array
(
[id] => 4065301
[patent_doc_number] => 05970011
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Power source design for embedded memory'
[patent_app_type] => 1
[patent_app_number] => 9/198900
[patent_app_country] => US
[patent_app_date] => 1998-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1382
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/970/05970011.pdf
[firstpage_image] =>[orig_patent_app_number] => 198900
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/198900 | Power source design for embedded memory | Nov 22, 1998 | Issued |