Richard M. Lorence

Array ( [id] => 4219367 [patent_doc_number] => 06028803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Read amplifier for semiconductor memory cells with means to compensate threshold voltage differences in read amplifier transistors' [patent_app_type] => 1 [patent_app_number] => 9/180665 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2532 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028803.pdf [firstpage_image] =>[orig_patent_app_number] => 180665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4096680 [patent_doc_number] => 06026017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Compact nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/189249 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4076 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026017.pdf [firstpage_image] =>[orig_patent_app_number] => 189249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4246329 [patent_doc_number] => 06075750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 9/186497 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3573 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075750.pdf [firstpage_image] =>[orig_patent_app_number] => 186497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250394 [patent_doc_number] => 06144584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Non-volatile semiconductor memory device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/184865 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 129 [patent_no_of_words] => 35890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144584.pdf [firstpage_image] =>[orig_patent_app_number] => 184865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4209375 [patent_doc_number] => 06014333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Semiconductive memory device capable of carrying out a write-in operation at a high speed' [patent_app_type] => 1 [patent_app_number] => 9/179098 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014333.pdf [firstpage_image] =>[orig_patent_app_number] => 179098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187727 [patent_doc_number] => 06084803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Initialization of non-volatile programmable latches in circuits in which an initialization operation is performed' [patent_app_type] => 1 [patent_app_number] => 9/178197 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3606 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084803.pdf [firstpage_image] =>[orig_patent_app_number] => 178197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144220 [patent_doc_number] => 06034889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Electrically erasable and programmable non-volatile memory having a protectable zone and an electronic system including the memory' [patent_app_type] => 1 [patent_app_number] => 9/177899 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034889.pdf [firstpage_image] =>[orig_patent_app_number] => 177899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6221824 [patent_doc_number] => 20020003241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'STATIC SEMICONDUCTOR MEMORY CELL FORMED IN AN N-WELL AND P-WELL' [patent_app_type] => new [patent_app_number] => 09/166906 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4687 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003241.pdf [firstpage_image] =>[orig_patent_app_number] => 09166906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4096593 [patent_doc_number] => 06026011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'CMOS latch design with soft error immunity' [patent_app_type] => 1 [patent_app_number] => 9/159465 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2370 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026011.pdf [firstpage_image] =>[orig_patent_app_number] => 159465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960733 [patent_doc_number] => 05991228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Semiconductor memory device having improved data output circuit' [patent_app_type] => 1 [patent_app_number] => 9/154097 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2959 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991228.pdf [firstpage_image] =>[orig_patent_app_number] => 154097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4154974 [patent_doc_number] => 06031753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Nonvolatile ferroelectric memory and circuit for controlling the same' [patent_app_type] => 1 [patent_app_number] => 9/150173 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2799 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031753.pdf [firstpage_image] =>[orig_patent_app_number] => 150173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4082628 [patent_doc_number] => 06069836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method and apparatus for a RAM circuit having N-nary word line generation' [patent_app_type] => 1 [patent_app_number] => 9/150162 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7641 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069836.pdf [firstpage_image] =>[orig_patent_app_number] => 150162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126684 [patent_doc_number] => 06046930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Memory array and method for writing data to memory' [patent_app_type] => 1 [patent_app_number] => 9/144871 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046930.pdf [firstpage_image] =>[orig_patent_app_number] => 144871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4229531 [patent_doc_number] => 06111773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Memory circuit having improved sense-amplifier block and method for forming same' [patent_app_type] => 1 [patent_app_number] => 9/143164 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5470 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111773.pdf [firstpage_image] =>[orig_patent_app_number] => 143164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131271 [patent_doc_number] => 06072729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Data-output driver circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/138861 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4129 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072729.pdf [firstpage_image] =>[orig_patent_app_number] => 138861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250282 [patent_doc_number] => 06144576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and apparatus for implementing a serial memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/136797 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7394 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144576.pdf [firstpage_image] =>[orig_patent_app_number] => 136797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159627 [patent_doc_number] => 06064612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method and circuit for high speed differential data transmission' [patent_app_type] => 1 [patent_app_number] => 9/126273 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4238 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064612.pdf [firstpage_image] =>[orig_patent_app_number] => 126273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4193998 [patent_doc_number] => 06021076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Apparatus and method for thermal regulation in memory subsystems' [patent_app_type] => 1 [patent_app_number] => 9/118696 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021076.pdf [firstpage_image] =>[orig_patent_app_number] => 118696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110121 [patent_doc_number] => 06097625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes' [patent_app_type] => 1 [patent_app_number] => 9/116261 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3742 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097625.pdf [firstpage_image] =>[orig_patent_app_number] => 116261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4096299 [patent_doc_number] => 06018482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'High efficiency redundancy scheme for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/110297 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 7770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018482.pdf [firstpage_image] =>[orig_patent_app_number] => 110297 [rel_patent_id] =>[rel_patent_doc_number] =>)