Richard M. Lorence

Array ( [id] => 4147886 [patent_doc_number] => 06122203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method, architecture and circuit for writing to and reading from a memory during a single cycle' [patent_app_type] => 1 [patent_app_number] => 9/107000 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122203.pdf [firstpage_image] =>[orig_patent_app_number] => 107000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159471 [patent_doc_number] => 06064601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Integrated circuit memory devices and controlling methods that simultaneously activate multiple column select lines during a write cycle of a parallel bit test mode' [patent_app_type] => 1 [patent_app_number] => 9/104475 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2384 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064601.pdf [firstpage_image] =>[orig_patent_app_number] => 104475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114859 [patent_doc_number] => 06052304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Non-volatile storage element and method for manufacturing using standard processing' [patent_app_type] => 1 [patent_app_number] => 9/099574 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5813 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052304.pdf [firstpage_image] =>[orig_patent_app_number] => 099574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204665 [patent_doc_number] => 06044018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Single-poly flash memory cell for embedded application and related methods' [patent_app_type] => 1 [patent_app_number] => 9/107172 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3251 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044018.pdf [firstpage_image] =>[orig_patent_app_number] => 107172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250472 [patent_doc_number] => 06081451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages' [patent_app_type] => 1 [patent_app_number] => 9/082145 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7145 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081451.pdf [firstpage_image] =>[orig_patent_app_number] => 082145 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317239 [patent_doc_number] => 06188633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations' [patent_app_type] => 1 [patent_app_number] => 9/067702 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7345 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188633.pdf [firstpage_image] =>[orig_patent_app_number] => 067702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4065212 [patent_doc_number] => 05970005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Testing structure and method for high density PLDs which have flexible logic built-in blocks' [patent_app_type] => 1 [patent_app_number] => 9/069016 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7427 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970005.pdf [firstpage_image] =>[orig_patent_app_number] => 069016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953647 [patent_doc_number] => 05973990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Synchronous semiconductor memory device including a circuit for arbitrarily controlling activation/inactivation timing of word line' [patent_app_type] => 1 [patent_app_number] => 9/060311 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 73 [patent_no_of_words] => 15131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973990.pdf [firstpage_image] =>[orig_patent_app_number] => 060311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298477 [patent_doc_number] => 06269027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Non-volatile storage latch' [patent_app_type] => 1 [patent_app_number] => 9/059871 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5425 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269027.pdf [firstpage_image] =>[orig_patent_app_number] => 059871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110700 [patent_doc_number] => 06067255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Merged memory and logic (MML) integrated circuits including independent memory bank signals and methods' [patent_app_type] => 1 [patent_app_number] => 9/059117 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4645 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067255.pdf [firstpage_image] =>[orig_patent_app_number] => 059117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110646 [patent_doc_number] => 06097660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/053511 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8919 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097660.pdf [firstpage_image] =>[orig_patent_app_number] => 053511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4093403 [patent_doc_number] => 06055185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Single-poly EPROM cell with CMOS compatible programming voltages' [patent_app_type] => 1 [patent_app_number] => 9/053309 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3697 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055185.pdf [firstpage_image] =>[orig_patent_app_number] => 053309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191830 [patent_doc_number] => 06038166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'High resolution multi-bit-per-cell memory' [patent_app_type] => 1 [patent_app_number] => 9/053716 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9057 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038166.pdf [firstpage_image] =>[orig_patent_app_number] => 053716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120605 [patent_doc_number] => 06058055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'System for testing memory' [patent_app_type] => 1 [patent_app_number] => 9/053403 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058055.pdf [firstpage_image] =>[orig_patent_app_number] => 053403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3997909 [patent_doc_number] => 05959879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Ferroelectric memory devices having well region word lines and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/052533 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3146 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959879.pdf [firstpage_image] =>[orig_patent_app_number] => 052533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969960 [patent_doc_number] => 05936882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Magnetoresistive random access memory device and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/053900 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4875 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936882.pdf [firstpage_image] =>[orig_patent_app_number] => 053900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4012560 [patent_doc_number] => 05986967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Power saving synchronization circuit and semiconductor storage device including the same' [patent_app_type] => 1 [patent_app_number] => 9/050030 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6333 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986967.pdf [firstpage_image] =>[orig_patent_app_number] => 050030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937108 [patent_doc_number] => 05946236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Non-volatile semiconductor memory device and method for writing information therein' [patent_app_type] => 1 [patent_app_number] => 9/049307 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3897 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946236.pdf [firstpage_image] =>[orig_patent_app_number] => 049307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4086391 [patent_doc_number] => 05966338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Dram with new I/O data path configuration' [patent_app_type] => 1 [patent_app_number] => 9/047304 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3643 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 507 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966338.pdf [firstpage_image] =>[orig_patent_app_number] => 047304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957377 [patent_doc_number] => 05982683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Enhanced method of testing semiconductor devices having nonvolatile elements' [patent_app_type] => 1 [patent_app_number] => 9/046404 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7545 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982683.pdf [firstpage_image] =>[orig_patent_app_number] => 046404 [rel_patent_id] =>[rel_patent_doc_number] =>)