Search

Richard R. Roseen

Examiner (ID: 3481)

Most Active Art Unit
2509
Art Unit(s)
2504, 2819, 2509
Total Applications
956
Issued Applications
879
Pending Applications
14
Abandoned Applications
63

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4104872 [patent_doc_number] => 06049227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'FPGA with a plurality of I/O voltage levels' [patent_app_type] => 1 [patent_app_number] => 9/187666 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6042 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049227.pdf [firstpage_image] =>[orig_patent_app_number] => 187666 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187666
FPGA with a plurality of I/O voltage levels Nov 4, 1998 Issued
Array ( [id] => 3933962 [patent_doc_number] => 05952845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Semiconductor programmable test arrangement such as an antifuse ID circuit having common access switches and/or common programming switches' [patent_app_type] => 1 [patent_app_number] => 9/144807 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952845.pdf [firstpage_image] =>[orig_patent_app_number] => 144807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144807
Semiconductor programmable test arrangement such as an antifuse ID circuit having common access switches and/or common programming switches Aug 31, 1998 Issued
Array ( [id] => 4163644 [patent_doc_number] => 06104209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Low skew differential receiver with disable feature' [patent_app_type] => 1 [patent_app_number] => 9/140857 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2660 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104209.pdf [firstpage_image] =>[orig_patent_app_number] => 140857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140857
Low skew differential receiver with disable feature Aug 26, 1998 Issued
Array ( [id] => 4213998 [patent_doc_number] => 06028446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Flexible synchronous and asynchronous circuits for a very high density programmable logic device' [patent_app_type] => 1 [patent_app_number] => 9/118200 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 34 [patent_no_of_words] => 19068 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028446.pdf [firstpage_image] =>[orig_patent_app_number] => 118200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118200
Flexible synchronous and asynchronous circuits for a very high density programmable logic device Jul 16, 1998 Issued
Array ( [id] => 3931284 [patent_doc_number] => 05945845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method and apparatus for enhanced booting and DC conditions' [patent_app_type] => 1 [patent_app_number] => 9/112905 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2506 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945845.pdf [firstpage_image] =>[orig_patent_app_number] => 112905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112905
Method and apparatus for enhanced booting and DC conditions Jul 8, 1998 Issued
09/104465 COMPOSABLE MEMORY ARRAY FOR A PROGRAMMABLE LOGIC DEVICE AND METHOD FOR IMPLEMENTING SAME Jun 24, 1998 Issued
Array ( [id] => 4413198 [patent_doc_number] => 06172517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission' [patent_app_type] => 1 [patent_app_number] => 9/084017 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 52 [patent_no_of_words] => 10265 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172517.pdf [firstpage_image] =>[orig_patent_app_number] => 084017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084017
Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission May 25, 1998 Issued
Array ( [id] => 4245684 [patent_doc_number] => 06081133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Universal receiver device' [patent_app_type] => 1 [patent_app_number] => 9/073958 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4839 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081133.pdf [firstpage_image] =>[orig_patent_app_number] => 073958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073958
Universal receiver device May 6, 1998 Issued
Array ( [id] => 4023186 [patent_doc_number] => 05907248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'FPGA interconnect structure with high-speed high fanout capability' [patent_app_type] => 1 [patent_app_number] => 9/020369 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13847 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907248.pdf [firstpage_image] =>[orig_patent_app_number] => 020369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020369
FPGA interconnect structure with high-speed high fanout capability Feb 8, 1998 Issued
Array ( [id] => 4040487 [patent_doc_number] => 05994921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Universal sender device' [patent_app_type] => 1 [patent_app_number] => 9/015549 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3392 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994921.pdf [firstpage_image] =>[orig_patent_app_number] => 015549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015549
Universal sender device Jan 28, 1998 Issued
Array ( [id] => 3919875 [patent_doc_number] => 06002269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'TTL logic driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/996866 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2119 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002269.pdf [firstpage_image] =>[orig_patent_app_number] => 996866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996866
TTL logic driver circuit Dec 22, 1997 Issued
Array ( [id] => 4149656 [patent_doc_number] => 06031390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Asynchronous registers with embedded acknowledge collection' [patent_app_type] => 1 [patent_app_number] => 8/991141 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7677 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031390.pdf [firstpage_image] =>[orig_patent_app_number] => 991141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991141
Asynchronous registers with embedded acknowledge collection Dec 15, 1997 Issued
Array ( [id] => 4186521 [patent_doc_number] => 06037803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Integrated circuit having two modes of I/O pad termination' [patent_app_type] => 1 [patent_app_number] => 8/990060 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4531 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037803.pdf [firstpage_image] =>[orig_patent_app_number] => 990060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990060
Integrated circuit having two modes of I/O pad termination Dec 11, 1997 Issued
Array ( [id] => 4226218 [patent_doc_number] => 06040714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method for providing two modes of I/O pad termination' [patent_app_type] => 1 [patent_app_number] => 8/990057 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4746 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040714.pdf [firstpage_image] =>[orig_patent_app_number] => 990057 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990057
Method for providing two modes of I/O pad termination Dec 11, 1997 Issued
Array ( [id] => 4005151 [patent_doc_number] => 05986468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Programmable application specific integrated circuit and logic cell therefor' [patent_app_type] => 1 [patent_app_number] => 8/988432 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6731 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 649 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986468.pdf [firstpage_image] =>[orig_patent_app_number] => 988432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988432
Programmable application specific integrated circuit and logic cell therefor Dec 10, 1997 Issued
Array ( [id] => 3946394 [patent_doc_number] => 05973512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'CMOS output buffer having load independent slewing' [patent_app_type] => 1 [patent_app_number] => 8/982959 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3717 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973512.pdf [firstpage_image] =>[orig_patent_app_number] => 982959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982959
CMOS output buffer having load independent slewing Dec 1, 1997 Issued
Array ( [id] => 4077492 [patent_doc_number] => 06069493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Input circuit and method for protecting the input circuit' [patent_app_type] => 1 [patent_app_number] => 8/980250 [patent_app_country] => US [patent_app_date] => 1997-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1936 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069493.pdf [firstpage_image] =>[orig_patent_app_number] => 980250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980250
Input circuit and method for protecting the input circuit Nov 27, 1997 Issued
Array ( [id] => 3991116 [patent_doc_number] => 05910733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Method and system for layout and schematic generation for heterogeneous arrays' [patent_app_type] => 1 [patent_app_number] => 8/968543 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5461 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910733.pdf [firstpage_image] =>[orig_patent_app_number] => 968543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968543
Method and system for layout and schematic generation for heterogeneous arrays Nov 11, 1997 Issued
Array ( [id] => 3803773 [patent_doc_number] => 05828232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Circuit to reduce current and voltage spikes when switching inductive loads' [patent_app_type] => 1 [patent_app_number] => 8/966594 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 8033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828232.pdf [firstpage_image] =>[orig_patent_app_number] => 966594 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966594
Circuit to reduce current and voltage spikes when switching inductive loads Nov 9, 1997 Issued
Array ( [id] => 3812942 [patent_doc_number] => 05854561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Switched substrate bias for MOS DRAM circuits' [patent_app_type] => 1 [patent_app_number] => 8/957426 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14108 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854561.pdf [firstpage_image] =>[orig_patent_app_number] => 957426 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957426
Switched substrate bias for MOS DRAM circuits Oct 23, 1997 Issued
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