Search

Richard R. Roseen

Examiner (ID: 15795)

Most Active Art Unit
2509
Art Unit(s)
2504, 2819, 2509
Total Applications
956
Issued Applications
879
Pending Applications
14
Abandoned Applications
63

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3948497 [patent_doc_number] => RE036292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit' [patent_app_type] => 2 [patent_app_number] => 8/876130 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3916 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036292.pdf [firstpage_image] =>[orig_patent_app_number] => 876130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876130
Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit Jun 22, 1997 Issued
Array ( [id] => 3931211 [patent_doc_number] => 05945840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Low current redundancy anti-fuse assembly' [patent_app_type] => 1 [patent_app_number] => 8/879983 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2981 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945840.pdf [firstpage_image] =>[orig_patent_app_number] => 879983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879983
Low current redundancy anti-fuse assembly Jun 19, 1997 Issued
Array ( [id] => 4072808 [patent_doc_number] => 06008669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Monolithic integrated multiple mode circuit' [patent_app_type] => 1 [patent_app_number] => 8/879835 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5052 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008669.pdf [firstpage_image] =>[orig_patent_app_number] => 879835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879835
Monolithic integrated multiple mode circuit Jun 18, 1997 Issued
Array ( [id] => 4058308 [patent_doc_number] => 05969544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/867851 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10262 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969544.pdf [firstpage_image] =>[orig_patent_app_number] => 867851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867851
Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit Jun 2, 1997 Issued
Array ( [id] => 3931298 [patent_doc_number] => 05945846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Clock driver circuit in a centrally located macro cell layout region' [patent_app_type] => 1 [patent_app_number] => 8/867391 [patent_app_country] => US [patent_app_date] => 1997-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12457 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945846.pdf [firstpage_image] =>[orig_patent_app_number] => 867391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867391
Clock driver circuit in a centrally located macro cell layout region Jun 1, 1997 Issued
Array ( [id] => 3876297 [patent_doc_number] => 05838167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method and structure for loading data into several IC devices' [patent_app_type] => 1 [patent_app_number] => 8/855029 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3156 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838167.pdf [firstpage_image] =>[orig_patent_app_number] => 855029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855029
Method and structure for loading data into several IC devices May 12, 1997 Issued
Array ( [id] => 3822899 [patent_doc_number] => 05789940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Reduced complexity multiple resonant tunneling circuits for positive digit multivalued logic operations' [patent_app_type] => 1 [patent_app_number] => 8/834785 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4755 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789940.pdf [firstpage_image] =>[orig_patent_app_number] => 834785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834785
Reduced complexity multiple resonant tunneling circuits for positive digit multivalued logic operations Apr 2, 1997 Issued
Array ( [id] => 3881503 [patent_doc_number] => 05764084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Time multiplexed ratioed logic' [patent_app_type] => 1 [patent_app_number] => 8/819179 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 16656 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764084.pdf [firstpage_image] =>[orig_patent_app_number] => 819179 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819179
Time multiplexed ratioed logic Mar 16, 1997 Issued
Array ( [id] => 4021307 [patent_doc_number] => 05880601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Signal receiving circuit and digital signal processing system' [patent_app_type] => 1 [patent_app_number] => 8/750581 [patent_app_country] => US [patent_app_date] => 1997-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5828 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880601.pdf [firstpage_image] =>[orig_patent_app_number] => 750581 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/750581
Signal receiving circuit and digital signal processing system Feb 26, 1997 Issued
Array ( [id] => 3991730 [patent_doc_number] => 05959466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Field programmable gate array with mask programmed input and output buffers' [patent_app_type] => 1 [patent_app_number] => 8/792482 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5972 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959466.pdf [firstpage_image] =>[orig_patent_app_number] => 792482 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792482
Field programmable gate array with mask programmed input and output buffers Jan 30, 1997 Issued
Array ( [id] => 3999952 [patent_doc_number] => 05892373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Distributed gated clock driver' [patent_app_type] => 1 [patent_app_number] => 8/790393 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2635 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892373.pdf [firstpage_image] =>[orig_patent_app_number] => 790393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790393
Distributed gated clock driver Jan 28, 1997 Issued
Array ( [id] => 4032385 [patent_doc_number] => 05883527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Tri-state output circuit for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/789797 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883527.pdf [firstpage_image] =>[orig_patent_app_number] => 789797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789797
Tri-state output circuit for semiconductor device Jan 27, 1997 Issued
Array ( [id] => 4004552 [patent_doc_number] => 05923187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Multidirectional data transmission device' [patent_app_type] => 1 [patent_app_number] => 8/785457 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4605 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923187.pdf [firstpage_image] =>[orig_patent_app_number] => 785457 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785457
Multidirectional data transmission device Jan 16, 1997 Issued
Array ( [id] => 4021266 [patent_doc_number] => 05880598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Tile-based modular routing resources for high density programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/781251 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5713 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880598.pdf [firstpage_image] =>[orig_patent_app_number] => 781251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781251
Tile-based modular routing resources for high density programmable logic device Jan 9, 1997 Issued
Array ( [id] => 3847227 [patent_doc_number] => 05847578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Programmable multiplexing input/output port' [patent_app_type] => 1 [patent_app_number] => 8/780527 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3540 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847578.pdf [firstpage_image] =>[orig_patent_app_number] => 780527 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780527
Programmable multiplexing input/output port Jan 7, 1997 Issued
Array ( [id] => 3999907 [patent_doc_number] => 05892370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Clock network for field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/781985 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1733 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892370.pdf [firstpage_image] =>[orig_patent_app_number] => 781985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781985
Clock network for field programmable gate array Jan 2, 1997 Issued
Array ( [id] => 3784410 [patent_doc_number] => 05818253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission' [patent_app_type] => 1 [patent_app_number] => 8/773753 [patent_app_country] => US [patent_app_date] => 1996-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 52 [patent_no_of_words] => 10267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818253.pdf [firstpage_image] =>[orig_patent_app_number] => 773753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773753
Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission Dec 23, 1996 Issued
Array ( [id] => 4104045 [patent_doc_number] => 06097221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Semiconductor integrated circuit capable of realizing logic functions' [patent_app_type] => 1 [patent_app_number] => 8/763264 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 57 [patent_no_of_words] => 29407 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097221.pdf [firstpage_image] =>[orig_patent_app_number] => 763264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763264
Semiconductor integrated circuit capable of realizing logic functions Dec 9, 1996 Issued
Array ( [id] => 3784561 [patent_doc_number] => 05818262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'High speed CMOS output buffer using 3 volt or lower supply voltage supplied on a plurality of bond pads' [patent_app_type] => 1 [patent_app_number] => 8/758312 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818262.pdf [firstpage_image] =>[orig_patent_app_number] => 758312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758312
High speed CMOS output buffer using 3 volt or lower supply voltage supplied on a plurality of bond pads Dec 2, 1996 Issued
Array ( [id] => 3859548 [patent_doc_number] => 05767695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Fast transmission line implemented with receiver, driver, terminator and IC arrangements' [patent_app_type] => 1 [patent_app_number] => 8/747208 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 52 [patent_no_of_words] => 10289 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767695.pdf [firstpage_image] =>[orig_patent_app_number] => 747208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747208
Fast transmission line implemented with receiver, driver, terminator and IC arrangements Nov 11, 1996 Issued
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