Richard R. Roseen

Array ( [id] => 3817759 [patent_doc_number] => 05811987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Block clock and initialization circuit for a complex high density PLD' [patent_app_type] => 1 [patent_app_number] => 8/740948 [patent_app_country] => US [patent_app_date] => 1996-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 16084 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811987.pdf [firstpage_image] =>[orig_patent_app_number] => 740948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882106 [patent_doc_number] => 05825197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/742770 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6851 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825197.pdf [firstpage_image] =>[orig_patent_app_number] => 742770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3881355 [patent_doc_number] => 05764075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Input circuit for mode setting' [patent_app_type] => 1 [patent_app_number] => 8/736498 [patent_app_country] => US [patent_app_date] => 1996-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4137 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764075.pdf [firstpage_image] =>[orig_patent_app_number] => 736498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836844 [patent_doc_number] => 05760603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'High speed PLD \"AND\" array with separate nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 8/729079 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4159 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760603.pdf [firstpage_image] =>[orig_patent_app_number] => 729079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767353 [patent_doc_number] => 05852370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Integrated circuits for low power dissipation in signaling between different-voltage on chip regions' [patent_app_type] => 1 [patent_app_number] => 8/728404 [patent_app_country] => US [patent_app_date] => 1996-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 79 [patent_no_of_words] => 92364 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852370.pdf [firstpage_image] =>[orig_patent_app_number] => 728404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3832318 [patent_doc_number] => 05783948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and apparatus for enhanced booting and DC conditions' [patent_app_type] => 1 [patent_app_number] => 8/729729 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2504 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783948.pdf [firstpage_image] =>[orig_patent_app_number] => 729729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3791129 [patent_doc_number] => 05821774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure' [patent_app_type] => 1 [patent_app_number] => 8/726115 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3584 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821774.pdf [firstpage_image] =>[orig_patent_app_number] => 726115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836871 [patent_doc_number] => 05760605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Programmable high speed routing switch' [patent_app_type] => 1 [patent_app_number] => 8/723082 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760605.pdf [firstpage_image] =>[orig_patent_app_number] => 723082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081958 [patent_doc_number] => 05966032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'BiCMOS transceiver (driver and receiver) for gigahertz operation' [patent_app_type] => 1 [patent_app_number] => 8/720377 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5142 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966032.pdf [firstpage_image] =>[orig_patent_app_number] => 720377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3887048 [patent_doc_number] => 05798657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Bidirectional driver circuit for PCI bus systems' [patent_app_type] => 1 [patent_app_number] => 8/722485 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2956 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798657.pdf [firstpage_image] =>[orig_patent_app_number] => 722485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3777718 [patent_doc_number] => 05773993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable electronic device' [patent_app_type] => 1 [patent_app_number] => 8/721387 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5477 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773993.pdf [firstpage_image] =>[orig_patent_app_number] => 721387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882184 [patent_doc_number] => 05825202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Integrated circuit with field programmable and application specific logic areas' [patent_app_type] => 1 [patent_app_number] => 8/721392 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825202.pdf [firstpage_image] =>[orig_patent_app_number] => 721392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049935 [patent_doc_number] => 05874835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'High impedance detecting circuit and interface circuit' [patent_app_type] => 1 [patent_app_number] => 8/719888 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 82 [patent_no_of_words] => 13340 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874835.pdf [firstpage_image] =>[orig_patent_app_number] => 719888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944566 [patent_doc_number] => 05872463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Routing in programmable logic devices using shared distributed programmable logic connectors' [patent_app_type] => 1 [patent_app_number] => 8/710862 [patent_app_country] => US [patent_app_date] => 1996-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3631 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872463.pdf [firstpage_image] =>[orig_patent_app_number] => 710862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3782312 [patent_doc_number] => 05808483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Logic circuit utilizing pass transistors and logic gate' [patent_app_type] => 1 [patent_app_number] => 8/716883 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 46 [patent_no_of_words] => 18971 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808483.pdf [firstpage_image] =>[orig_patent_app_number] => 716883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3728436 [patent_doc_number] => 05682106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Logic module for field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/755758 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 8077 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682106.pdf [firstpage_image] =>[orig_patent_app_number] => 755758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4063380 [patent_doc_number] => 05864243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Buffer and method for transferring data therein' [patent_app_type] => 1 [patent_app_number] => 8/715457 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4451 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864243.pdf [firstpage_image] =>[orig_patent_app_number] => 715457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3876332 [patent_doc_number] => 05838170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'PMOS charge-sharing prevention device for dynamic logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/713883 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2275 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838170.pdf [firstpage_image] =>[orig_patent_app_number] => 713883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3876320 [patent_doc_number] => 05838169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'NMOS charge-sharing prevention device for dynamic logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/713881 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2303 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838169.pdf [firstpage_image] =>[orig_patent_app_number] => 713881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767283 [patent_doc_number] => 05852365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Variable logic circuit and semiconductor integrated circuit using the same' [patent_app_type] => 1 [patent_app_number] => 8/712554 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 5374 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852365.pdf [firstpage_image] =>[orig_patent_app_number] => 712554 [rel_patent_id] =>[rel_patent_doc_number] =>)