Richard R. Roseen

Array ( [id] => 3796420 [patent_doc_number] => 05841298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Locally asynchronous, pipeline-able logic circuits for true-single-phase synchronous logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/637468 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 13931 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841298.pdf [firstpage_image] =>[orig_patent_app_number] => 637468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3956825 [patent_doc_number] => 05977799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Decoding circuit for a storing circuit' [patent_app_type] => 1 [patent_app_number] => 8/635879 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977799.pdf [firstpage_image] =>[orig_patent_app_number] => 635879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3817841 [patent_doc_number] => 05811992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Dynamic clocked inverter latch with reduced charged leakage and reduced body effect' [patent_app_type] => 1 [patent_app_number] => 8/639246 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811992.pdf [firstpage_image] =>[orig_patent_app_number] => 639246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3847534 [patent_doc_number] => 05744982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Input buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/636087 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2885 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 489 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744982.pdf [firstpage_image] =>[orig_patent_app_number] => 636087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3777749 [patent_doc_number] => 05773995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Digital multiplexer circuit' [patent_app_type] => 1 [patent_app_number] => 8/636084 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 10190 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773995.pdf [firstpage_image] =>[orig_patent_app_number] => 636084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894277 [patent_doc_number] => 05777488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Integrated circuit I/O node useable for configuration input at reset and normal output at other times' [patent_app_type] => 1 [patent_app_number] => 8/634879 [patent_app_country] => US [patent_app_date] => 1996-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3258 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777488.pdf [firstpage_image] =>[orig_patent_app_number] => 634879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884597 [patent_doc_number] => 05804990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Wired combinational logic circuit with pullup and pulldown devices' [patent_app_type] => 1 [patent_app_number] => 8/633985 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 8667 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804990.pdf [firstpage_image] =>[orig_patent_app_number] => 633985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3791037 [patent_doc_number] => 05821767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Information processing apparatus and backboard having on backboard side matching resistors suited to modules connected thereto' [patent_app_type] => 1 [patent_app_number] => 8/633309 [patent_app_country] => US [patent_app_date] => 1996-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 11784 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821767.pdf [firstpage_image] =>[orig_patent_app_number] => 633309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694146 [patent_doc_number] => 05663658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Low current redundancy fuse assembly' [patent_app_type] => 1 [patent_app_number] => 8/631449 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1678 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663658.pdf [firstpage_image] =>[orig_patent_app_number] => 631449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3752378 [patent_doc_number] => 05717347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Logic circuit of the emitter-coupled type, operating at a low supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/631385 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4487 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717347.pdf [firstpage_image] =>[orig_patent_app_number] => 631385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3839007 [patent_doc_number] => 05815007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'More-than-one detector' [patent_app_type] => 1 [patent_app_number] => 8/632391 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4278 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815007.pdf [firstpage_image] =>[orig_patent_app_number] => 632391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867559 [patent_doc_number] => 05796269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Composable memory array for a programmable logic device and method for implementing same' [patent_app_type] => 1 [patent_app_number] => 8/631298 [patent_app_country] => US [patent_app_date] => 1996-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6373 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796269.pdf [firstpage_image] =>[orig_patent_app_number] => 631298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884527 [patent_doc_number] => 05804985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Programmable output buffer and method for programming' [patent_app_type] => 1 [patent_app_number] => 8/626590 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5314 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804985.pdf [firstpage_image] =>[orig_patent_app_number] => 626590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767092 [patent_doc_number] => 05742186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Asynchronous serial communication channel network' [patent_app_type] => 1 [patent_app_number] => 8/622092 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2885 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742186.pdf [firstpage_image] =>[orig_patent_app_number] => 622092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3666710 [patent_doc_number] => 05656953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Low overhead memory designs for IC terminals' [patent_app_type] => 1 [patent_app_number] => 8/622094 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 51 [patent_no_of_words] => 11532 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656953.pdf [firstpage_image] =>[orig_patent_app_number] => 622094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882212 [patent_doc_number] => 05825204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Apparatus and method for a party check logic circuit in a dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/619392 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825204.pdf [firstpage_image] =>[orig_patent_app_number] => 619392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3799055 [patent_doc_number] => 05726584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Virtual high density programmable integrated circuit having addressable shared memory cells' [patent_app_type] => 1 [patent_app_number] => 8/619286 [patent_app_country] => US [patent_app_date] => 1996-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 10455 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726584.pdf [firstpage_image] =>[orig_patent_app_number] => 619286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893235 [patent_doc_number] => 05894227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Level restoration circuit for pass logic devices' [patent_app_type] => 1 [patent_app_number] => 8/616682 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5965 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894227.pdf [firstpage_image] =>[orig_patent_app_number] => 616682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3837691 [patent_doc_number] => 05739703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'BiCMOS logic gate' [patent_app_type] => 1 [patent_app_number] => 8/613881 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739703.pdf [firstpage_image] =>[orig_patent_app_number] => 613881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4189217 [patent_doc_number] => 06020758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Partially reconfigurable programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/615341 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2674 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020758.pdf [firstpage_image] =>[orig_patent_app_number] => 615341 [rel_patent_id] =>[rel_patent_doc_number] =>)