Search

Richard Sukyoon Woo

Examiner (ID: 19431)

Most Active Art Unit
3745
Art Unit(s)
3745, 3629, 3639
Total Applications
372
Issued Applications
301
Pending Applications
50
Abandoned Applications
21

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7535710 [patent_doc_number] => 08049339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Semiconductor package having isolated inner lead' [patent_app_type] => utility [patent_app_number] => 12/276970 [patent_app_country] => US [patent_app_date] => 2008-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5015 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/049/08049339.pdf [firstpage_image] =>[orig_patent_app_number] => 12276970 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/276970
Semiconductor package having isolated inner lead Nov 23, 2008 Issued
Array ( [id] => 5572959 [patent_doc_number] => 20090140320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE NONVOLATILE MEMORY DEVICE INCLUDING GIVING AN UPPER PORTION OF AN INSULATING LAYER AN ETCHING SELECTIVITY WITH RESPECT TO A LOWER PORTION' [patent_app_type] => utility [patent_app_number] => 12/275369 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7063 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140320.pdf [firstpage_image] =>[orig_patent_app_number] => 12275369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/275369
Nonvolatile memory device and method of forming the nonvolatile memory device including giving an upper portion of an insulating layer an etching selectivity with respect to a lower portion Nov 20, 2008 Issued
Array ( [id] => 5561678 [patent_doc_number] => 20090134530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/274719 [patent_app_country] => US [patent_app_date] => 2008-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5405 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134530.pdf [firstpage_image] =>[orig_patent_app_number] => 12274719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/274719
WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME Nov 19, 2008 Abandoned
Array ( [id] => 5561642 [patent_doc_number] => 20090134494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/274590 [patent_app_country] => US [patent_app_date] => 2008-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134494.pdf [firstpage_image] =>[orig_patent_app_number] => 12274590 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/274590
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 19, 2008 Abandoned
Array ( [id] => 5275481 [patent_doc_number] => 20090127613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/274750 [patent_app_country] => US [patent_app_date] => 2008-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127613.pdf [firstpage_image] =>[orig_patent_app_number] => 12274750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/274750
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 19, 2008 Abandoned
Array ( [id] => 6518708 [patent_doc_number] => 20100123187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING TRENCH SHIELD ELECTRODE AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/271030 [patent_app_country] => US [patent_app_date] => 2008-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8518 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123187.pdf [firstpage_image] =>[orig_patent_app_number] => 12271030 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/271030
Contact structure for semiconductor device having trench shield electrode and method Nov 13, 2008 Issued
Array ( [id] => 4634925 [patent_doc_number] => 08013378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Memory device having additional selection transistors and main bit lines' [patent_app_type] => utility [patent_app_number] => 12/270170 [patent_app_country] => US [patent_app_date] => 2008-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 8345 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 445 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013378.pdf [firstpage_image] =>[orig_patent_app_number] => 12270170 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/270170
Memory device having additional selection transistors and main bit lines Nov 12, 2008 Issued
Array ( [id] => 8653483 [patent_doc_number] => 08373233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Highly N-type and P-type co-doping silicon for strain silicon application' [patent_app_type] => utility [patent_app_number] => 12/270700 [patent_app_country] => US [patent_app_date] => 2008-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6980 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12270700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/270700
Highly N-type and P-type co-doping silicon for strain silicon application Nov 12, 2008 Issued
Array ( [id] => 5275589 [patent_doc_number] => 20090127721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/270469 [patent_app_country] => US [patent_app_date] => 2008-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3401 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127721.pdf [firstpage_image] =>[orig_patent_app_number] => 12270469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/270469
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Nov 12, 2008 Abandoned
Array ( [id] => 6272281 [patent_doc_number] => 20100117237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'Silicided Trench Contact to Buried Conductive Layer' [patent_app_type] => utility [patent_app_number] => 12/269069 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20100117237.pdf [firstpage_image] =>[orig_patent_app_number] => 12269069 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269069
Silicided trench contact to buried conductive layer Nov 11, 2008 Issued
Array ( [id] => 5407458 [patent_doc_number] => 20090121356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/269349 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8081 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121356.pdf [firstpage_image] =>[orig_patent_app_number] => 12269349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269349
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Nov 11, 2008 Abandoned
Array ( [id] => 5407378 [patent_doc_number] => 20090121276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'NONVOLATILE MEMORY DEVICES WITH RECESSED WORD LINES' [patent_app_type] => utility [patent_app_number] => 12/267679 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3862 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121276.pdf [firstpage_image] =>[orig_patent_app_number] => 12267679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267679
NONVOLATILE MEMORY DEVICES WITH RECESSED WORD LINES Nov 9, 2008 Abandoned
Array ( [id] => 6304277 [patent_doc_number] => 20100109076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION' [patent_app_type] => utility [patent_app_number] => 12/264879 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7404 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109076.pdf [firstpage_image] =>[orig_patent_app_number] => 12264879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264879
STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION Nov 3, 2008 Abandoned
Array ( [id] => 5449801 [patent_doc_number] => 20090065837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING CAPACITOR FOR PERIPHERAL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/264490 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4742 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20090065837.pdf [firstpage_image] =>[orig_patent_app_number] => 12264490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264490
Semiconductor memory device having capacitor for peripheral circuit Nov 3, 2008 Issued
Array ( [id] => 7504703 [patent_doc_number] => 08035169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Semiconductor device with suppressed crystal defects in active areas' [patent_app_type] => utility [patent_app_number] => 12/262180 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 20568 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035169.pdf [firstpage_image] =>[orig_patent_app_number] => 12262180 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/262180
Semiconductor device with suppressed crystal defects in active areas Oct 30, 2008 Issued
Array ( [id] => 5452790 [patent_doc_number] => 20090068827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/289654 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6690 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068827.pdf [firstpage_image] =>[orig_patent_app_number] => 12289654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289654
Method for fabricating semiconductor device Oct 30, 2008 Abandoned
Array ( [id] => 7978551 [patent_doc_number] => 08072023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Isolation for non-volatile memory cell array' [patent_app_type] => utility [patent_app_number] => 12/262599 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7731 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072023.pdf [firstpage_image] =>[orig_patent_app_number] => 12262599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/262599
Isolation for non-volatile memory cell array Oct 30, 2008 Issued
Array ( [id] => 5389164 [patent_doc_number] => 20090206476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/262819 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2042 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206476.pdf [firstpage_image] =>[orig_patent_app_number] => 12262819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/262819
Conductive structure for a semiconductor integrated circuit Oct 30, 2008 Issued
Array ( [id] => 7527847 [patent_doc_number] => 08044442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Metal-insulator-metal (MIM) switching devices' [patent_app_type] => utility [patent_app_number] => 12/261865 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 11558 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/044/08044442.pdf [firstpage_image] =>[orig_patent_app_number] => 12261865 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261865
Metal-insulator-metal (MIM) switching devices Oct 29, 2008 Issued
Array ( [id] => 6304208 [patent_doc_number] => 20100109044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer' [patent_app_type] => utility [patent_app_number] => 12/261589 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109044.pdf [firstpage_image] =>[orig_patent_app_number] => 12261589 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261589
Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer Oct 29, 2008 Abandoned
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