Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3062973
[patent_doc_number] => 05283887
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-01
[patent_title] => 'Automatic document format conversion in an electronic mail system based upon user preference'
[patent_app_type] => 1
[patent_app_number] => 7/629926
[patent_app_country] => US
[patent_app_date] => 1990-12-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/629926 | Automatic document format conversion in an electronic mail system based upon user preference | Dec 18, 1990 | Issued |
07/633265 | VIRTUAL ADDRESSING OF OPTICAL STORAGE MEDIA AS MAGNETIC TAPE EQUIVALENTS | Dec 18, 1990 | Abandoned |
07/625648 | SYSTEM FOR THE AUTOMATIC TRANSFER OF MESSAGE STATUS IN DIGITAL DATA COMMUNICATION | Dec 6, 1990 | Abandoned |
Array
(
[id] => 3089951
[patent_doc_number] => 05297268
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'ID protected memory with a readable/writable ID template'
[patent_app_type] => 1
[patent_app_number] => 7/622297
[patent_app_country] => US
[patent_app_date] => 1990-12-04
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[pdf_file] => patents/05/297/05297268.pdf
[firstpage_image] =>[orig_patent_app_number] => 622297
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/622297 | ID protected memory with a readable/writable ID template | Dec 3, 1990 | Issued |
Array
(
[id] => 3050112
[patent_doc_number] => 05301305
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Apparatus for amplifying signals in ping-pong arrangement to reduce the frequency of amplification'
[patent_app_type] => 1
[patent_app_number] => 7/616988
[patent_app_country] => US
[patent_app_date] => 1990-11-20
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 616988
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/616988 | Apparatus for amplifying signals in ping-pong arrangement to reduce the frequency of amplification | Nov 19, 1990 | Issued |
07/603248 | VIRTUAL ADDRESS WRITE BACK CACHE WITH ADDRESS REASSIGNMENT AND CACHE BLOCK FLUSH | Oct 23, 1990 | Abandoned |
Array
(
[id] => 3024814
[patent_doc_number] => 05276870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'View composition in a data base management system'
[patent_app_type] => 1
[patent_app_number] => 7/595717
[patent_app_country] => US
[patent_app_date] => 1990-10-09
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 595717
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/595717 | View composition in a data base management system | Oct 8, 1990 | Issued |
Array
(
[id] => 3108582
[patent_doc_number] => 05293499
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Apparatus for executing a RISC store and RI instruction pair in two clock cycles'
[patent_app_type] => 1
[patent_app_number] => 7/588494
[patent_app_country] => US
[patent_app_date] => 1990-09-21
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[pdf_file] => patents/05/293/05293499.pdf
[firstpage_image] =>[orig_patent_app_number] => 588494
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/588494 | Apparatus for executing a RISC store and RI instruction pair in two clock cycles | Sep 20, 1990 | Issued |
Array
(
[id] => 2798894
[patent_doc_number] => 05155807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Multi-processor communications channel utilizing random access/sequential access memories'
[patent_app_type] => 1
[patent_app_number] => 7/582823
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[firstpage_image] =>[orig_patent_app_number] => 582823
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/582823 | Multi-processor communications channel utilizing random access/sequential access memories | Sep 13, 1990 | Issued |
Array
(
[id] => 3464991
[patent_doc_number] => 05379379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Memory control unit with selective execution of queued read and write requests'
[patent_app_type] => 1
[patent_app_number] => 7/580365
[patent_app_country] => US
[patent_app_date] => 1990-09-06
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[pdf_file] => patents/05/379/05379379.pdf
[firstpage_image] =>[orig_patent_app_number] => 580365
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/580365 | Memory control unit with selective execution of queued read and write requests | Sep 5, 1990 | Issued |
Array
(
[id] => 2948604
[patent_doc_number] => 05247662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Join processor for a relational database, using multiple auxiliary processors'
[patent_app_type] => 1
[patent_app_number] => 7/576202
[patent_app_country] => US
[patent_app_date] => 1990-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2868
[patent_no_of_claims] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/247/05247662.pdf
[firstpage_image] =>[orig_patent_app_number] => 576202
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/576202 | Join processor for a relational database, using multiple auxiliary processors | Aug 28, 1990 | Issued |
07/563941 | DATA TRANSFERRING BUFFER | Aug 5, 1990 | Abandoned |
07/560217 | MEMORY DEVICE HAVING A CHANGE CIRCUIT FOR DESIGNATING MEMORY REGIONS FOR A PREDETERMINED NUMBER OF DATA WRITING/ERASING OPERATIONS | Jul 24, 1990 | Abandoned |
Array
(
[id] => 3023501
[patent_doc_number] => 05276807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking'
[patent_app_type] => 1
[patent_app_number] => 7/556878
[patent_app_country] => US
[patent_app_date] => 1990-07-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/276/05276807.pdf
[firstpage_image] =>[orig_patent_app_number] => 556878
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/556878 | Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking | Jul 19, 1990 | Issued |
07/555660 | SYSTEM AND METHOD FOR CONTROLLING EXECUTION OF NESTED LOOPS IN PARALLEL IN A COMPUTER INCLUDING MULTIPLE PROCESSORS, AND COMPILER FOR GENERATION CODE THEREOF | Jul 17, 1990 | Abandoned |
Array
(
[id] => 2945241
[patent_doc_number] => 05233695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-03
[patent_title] => 'Microprocessor with a reduced size microprogram'
[patent_app_type] => 1
[patent_app_number] => 7/552841
[patent_app_country] => US
[patent_app_date] => 1990-07-16
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[pdf_file] => patents/05/233/05233695.pdf
[firstpage_image] =>[orig_patent_app_number] => 552841
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/552841 | Microprocessor with a reduced size microprogram | Jul 15, 1990 | Issued |
Array
(
[id] => 3050602
[patent_doc_number] => 05301329
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Double unequal bus timeout'
[patent_app_type] => 1
[patent_app_number] => 7/550206
[patent_app_country] => US
[patent_app_date] => 1990-07-09
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 550206
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/550206 | Double unequal bus timeout | Jul 8, 1990 | Issued |
Array
(
[id] => 2977015
[patent_doc_number] => 05265220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Address control device for effectively controlling an address storing operation even when a request is subsequently cancelled'
[patent_app_type] => 1
[patent_app_number] => 7/549623
[patent_app_country] => US
[patent_app_date] => 1990-07-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/549623 | Address control device for effectively controlling an address storing operation even when a request is subsequently cancelled | Jul 8, 1990 | Issued |
Array
(
[id] => 2976777
[patent_doc_number] => 05274781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Programmable controller module identification by interconnecting the input and output ports of a module in a predefined manner'
[patent_app_type] => 1
[patent_app_number] => 7/550247
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/550247 | Programmable controller module identification by interconnecting the input and output ports of a module in a predefined manner | Jul 5, 1990 | Issued |
Array
(
[id] => 3059540
[patent_doc_number] => 05287522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip'
[patent_app_type] => 1
[patent_app_number] => 7/546347
[patent_app_country] => US
[patent_app_date] => 1990-06-29
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[firstpage_image] =>[orig_patent_app_number] => 546347
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/546347 | External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip | Jun 28, 1990 | Issued |