Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 2980557
[patent_doc_number] => 05202996
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Software structuring system and method by data table translation'
[patent_app_type] => 1
[patent_app_number] => 7/527715
[patent_app_country] => US
[patent_app_date] => 1990-05-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/527715 | Software structuring system and method by data table translation | May 22, 1990 | Issued |
07/524711 | DATA TRANSMISSION CONTROL APPARATUS FOR SYSTEM WITH INPUT/OUTPUT UNITS USED IN COMMON BY SEVERAL CPU'S | May 20, 1990 | Abandoned |
07/521272 | TIMING GENERATOR | May 8, 1990 | Abandoned |
Array
(
[id] => 3850063
[patent_doc_number] => 05761493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Apparatus and method for adding an associative query capability to a programming language'
[patent_app_type] => 1
[patent_app_number] => 7/516369
[patent_app_country] => US
[patent_app_date] => 1990-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/761/05761493.pdf
[firstpage_image] =>[orig_patent_app_number] => 516369
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/516369 | Apparatus and method for adding an associative query capability to a programming language | Apr 29, 1990 | Issued |
07/517424 | HIGH BANDWIDTH MULTIPLE COMPUTER BUS APPARATUS | Apr 29, 1990 | Abandoned |
07/517542 | PIPELINE PROCESSING SYSTEM AND MICROPROCESSOR USING THE SYSTEM | Apr 26, 1990 | Abandoned |
Array
(
[id] => 3078018
[patent_doc_number] => 05295253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'Cache memory utilizing a two-phase synchronization signal for controlling saturation conditions of the cache'
[patent_app_type] => 1
[patent_app_number] => 7/508965
[patent_app_country] => US
[patent_app_date] => 1990-04-12
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[firstpage_image] =>[orig_patent_app_number] => 508965
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/508965 | Cache memory utilizing a two-phase synchronization signal for controlling saturation conditions of the cache | Apr 11, 1990 | Issued |
Array
(
[id] => 3106838
[patent_doc_number] => 05369761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Automatic and transparent denormalization support, wherein denormalization is achieved through appending of fields to base relations of a normalized database'
[patent_app_type] => 1
[patent_app_number] => 7/502351
[patent_app_country] => US
[patent_app_date] => 1990-03-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/502351 | Automatic and transparent denormalization support, wherein denormalization is achieved through appending of fields to base relations of a normalized database | Mar 29, 1990 | Issued |
Array
(
[id] => 2998584
[patent_doc_number] => 05251299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'System for switching between processors in a multiprocessor system'
[patent_app_type] => 1
[patent_app_number] => 7/523823
[patent_app_country] => US
[patent_app_date] => 1990-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 51
[patent_no_of_words] => 10782
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[pdf_file] => patents/05/251/05251299.pdf
[firstpage_image] =>[orig_patent_app_number] => 523823
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/523823 | System for switching between processors in a multiprocessor system | Mar 18, 1990 | Issued |
07/485917 | NATURAL LANGUAGE ANALYZING APPARATUS AND METHOD | Feb 26, 1990 | Abandoned |
Array
(
[id] => 2914079
[patent_doc_number] => 05218695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-08
[patent_title] => 'File server system having high-speed write execution'
[patent_app_type] => 1
[patent_app_number] => 7/475368
[patent_app_country] => US
[patent_app_date] => 1990-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/218/05218695.pdf
[firstpage_image] =>[orig_patent_app_number] => 475368
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/475368 | File server system having high-speed write execution | Feb 4, 1990 | Issued |
07/461165 | HIGH SPEED ACTIVE BUS | Jan 4, 1990 | Abandoned |
07/459410 | METHOD FOR UNBLOCKING A MULTIBUS MULTIPROCESSOR SYSTEM | Dec 28, 1989 | Abandoned |
Array
(
[id] => 3058482
[patent_doc_number] => 05287469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Electrically erasable and programmable non-volatile memory (EEPROM), wherein write pulses can be interrupted by subsequently received read requests'
[patent_app_type] => 1
[patent_app_number] => 7/457245
[patent_app_country] => US
[patent_app_date] => 1989-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4534
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/287/05287469.pdf
[firstpage_image] =>[orig_patent_app_number] => 457245
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/457245 | Electrically erasable and programmable non-volatile memory (EEPROM), wherein write pulses can be interrupted by subsequently received read requests | Dec 26, 1989 | Issued |
Array
(
[id] => 3025008
[patent_doc_number] => 05276880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Method for parsing and representing multi-versioned computer programs, for simultaneous and synchronous processing of the plural parses'
[patent_app_type] => 1
[patent_app_number] => 7/451493
[patent_app_country] => US
[patent_app_date] => 1989-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/276/05276880.pdf
[firstpage_image] =>[orig_patent_app_number] => 451493
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/451493 | Method for parsing and representing multi-versioned computer programs, for simultaneous and synchronous processing of the plural parses | Dec 14, 1989 | Issued |
Array
(
[id] => 3023757
[patent_doc_number] => 05276819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Horizontal computer having register multiconnect for operand address generation during execution of iterations of a loop of program code'
[patent_app_type] => 1
[patent_app_number] => 7/445136
[patent_app_country] => US
[patent_app_date] => 1989-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 23311
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[pdf_file] => patents/05/276/05276819.pdf
[firstpage_image] =>[orig_patent_app_number] => 445136
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/445136 | Horizontal computer having register multiconnect for operand address generation during execution of iterations of a loop of program code | Nov 29, 1989 | Issued |
Array
(
[id] => 3071299
[patent_doc_number] => 05339447
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-16
[patent_title] => 'Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data'
[patent_app_type] => 1
[patent_app_number] => 7/437857
[patent_app_country] => US
[patent_app_date] => 1989-11-17
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[pdf_file] => patents/05/339/05339447.pdf
[firstpage_image] =>[orig_patent_app_number] => 437857
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/437857 | Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data | Nov 16, 1989 | Issued |
Array
(
[id] => 2902010
[patent_doc_number] => 05239649
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-24
[patent_title] => 'Channel path load balancing, through selection of storage volumes to be processed, for long running applications'
[patent_app_type] => 1
[patent_app_number] => 7/428542
[patent_app_country] => US
[patent_app_date] => 1989-10-30
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[firstpage_image] =>[orig_patent_app_number] => 428542
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/428542 | Channel path load balancing, through selection of storage volumes to be processed, for long running applications | Oct 29, 1989 | Issued |
Array
(
[id] => 2908339
[patent_doc_number] => 05241671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Multimedia search system using a plurality of entry path means which indicate interrelatedness of information'
[patent_app_type] => 1
[patent_app_number] => 7/426917
[patent_app_country] => US
[patent_app_date] => 1989-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[firstpage_image] =>[orig_patent_app_number] => 426917
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/426917 | Multimedia search system using a plurality of entry path means which indicate interrelatedness of information | Oct 25, 1989 | Issued |
07/419593 | MULTIPLE STEP DATA READ APPARATUS | Oct 9, 1989 | Abandoned |