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Ricky D Shafer

Examiner (ID: 1276, Phone: (571)272-2320 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2872, 2507
Total Applications
2433
Issued Applications
1743
Pending Applications
161
Abandoned Applications
529
Applications
StatisticsSubscription-Only

Applications

Application numberTitle of the applicationFiling DateStatus
07/249789 CONTROL SYSTEM OF DATA CACHE MEMORY Sep 26, 1988 Abandoned
Array ( [id] => 2702998 [patent_doc_number] => 05065314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Method and circuit for automatically communicating in two modes through a backplane' [patent_app_type] => 1 [patent_app_number] => 7/249415 [patent_app_country] => US [patent_app_date] => 1988-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13333 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065314.pdf [firstpage_image] =>[orig_patent_app_number] => 249415 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/249415 		Method and circuit for automatically communicating in two modes through a backplane Sep 22, 1988 Issued
07/246975 GENERIC CODE SHARING ARRANGEMENT FOR DIGITAL DATA PROCESSING SYSTEM Sep 19, 1988 Abandoned
Array ( [id] => 2743741 [patent_doc_number] => 05051946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Integrated scannable rotational priority network apparatus' [patent_app_type] => 1 [patent_app_number] => 7/244189 [patent_app_country] => US [patent_app_date] => 1988-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3849 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051946.pdf [firstpage_image] =>[orig_patent_app_number] => 244189 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/244189 		Integrated scannable rotational priority network apparatus Sep 12, 1988 Issued
Array ( [id] => 2633516 [patent_doc_number] => 04920485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Method and apparatus for arbitration and serialization in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/239067 [patent_app_country] => US [patent_app_date] => 1988-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4440 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920485.pdf [firstpage_image] =>[orig_patent_app_number] => 239067 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/239067 		Method and apparatus for arbitration and serialization in a multiprocessor system Aug 30, 1988 Issued
07/222767 SYSTEM FOR THE INVALIDATION PROCESS FOR THE ADDRESS TRANSFORMATION BUFFER AND METHOD OF THE PROCESS Jul 21, 1988 Abandoned
Array ( [id] => 3024731 [patent_doc_number] => 05276866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'System with two different communication mediums, transmitting retrieved video and compressed audio information to plural receivers responsively to users\' requests' [patent_app_type] => 1 [patent_app_number] => 7/221331 [patent_app_country] => US [patent_app_date] => 1988-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276866.pdf [firstpage_image] =>[orig_patent_app_number] => 221331 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/221331 		System with two different communication mediums, transmitting retrieved video and compressed audio information to plural receivers responsively to users' requests Jul 18, 1988 Issued
Array ( [id] => 2794018 [patent_doc_number] => 05093779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Computer file system' [patent_app_type] => 1 [patent_app_number] => 7/214461 [patent_app_country] => US [patent_app_date] => 1988-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6464 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093779.pdf [firstpage_image] =>[orig_patent_app_number] => 214461 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/214461 		Computer file system Jun 30, 1988 Issued
07/213395 MEMORY CONTROL UNIT Jun 29, 1988 Abandoned
07/212348 OPERAND SPECIFIER PROCESSING Jun 26, 1988 Abandoned
07/208520 DYNAMIC FORMAT CODE SCANNING Jun 14, 1988 Abandoned
07/202874 ID PROTECTED MEMORY WITH A READABLE/WRITABLE ID TEMPLATE Jun 2, 1988 Abandoned
Array ( [id] => 2816082 [patent_doc_number] => 05125084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller' [patent_app_type] => 1 [patent_app_number] => 7/198894 [patent_app_country] => US [patent_app_date] => 1988-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5895 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/125/05125084.pdf [firstpage_image] =>[orig_patent_app_number] => 198894 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/198894 		Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller May 25, 1988 Issued
Array ( [id] => 2842823 [patent_doc_number] => 05175826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385' [patent_app_type] => 1 [patent_app_number] => 7/198890 [patent_app_country] => US [patent_app_date] => 1988-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4595 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175826.pdf [firstpage_image] =>[orig_patent_app_number] => 198890 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/198890 		Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 May 25, 1988 Issued
Array ( [id] => 2844165 [patent_doc_number] => 05129090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration' [patent_app_type] => 1 [patent_app_number] => 7/198895 [patent_app_country] => US [patent_app_date] => 1988-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6013 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129090.pdf [firstpage_image] =>[orig_patent_app_number] => 198895 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/198895 		System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration May 25, 1988 Issued
07/198893 METHOD AND APPARATUS FOR SELECTIVELY POSTING WRITE CYCLES USING THE 82385 CACHE CONTROLLER May 25, 1988 Abandoned
07/195215 SYSTEM FOR THE AUTOMATIC TRANSFER OF MESSAGE STATUS IN DIGITAL DATA COMMUNICATION May 17, 1988 Abandoned
07/194613 INTERPROCESSOR COMMUNICATION SYSTEM IN INFORMATION PROCESSING SYSTEM ENABLING COMMUNICATION BETWEEN EXECUTION PROCESSOR UNITS DURING COMMUNICATION BETWEEN OTHER PROCESSOR UNITS May 15, 1988 Abandoned
07/192651 DOUBLE UNEQUAL BUS TIMEOUT May 10, 1988 Abandoned
Array ( [id] => 2588562 [patent_doc_number] => 04974156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-27 [patent_title] => 'Multi-level peripheral data storage hierarchy with independent access to all levels of the hierarchy' [patent_app_type] => 1 [patent_app_number] => 7/190421 [patent_app_country] => US [patent_app_date] => 1988-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4475 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/974/04974156.pdf [firstpage_image] =>[orig_patent_app_number] => 190421 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/190421 		Multi-level peripheral data storage hierarchy with independent access to all levels of the hierarchy May 4, 1988 Issued
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