
Robert A. Rose
Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )
| Most Active Art Unit | 3723 |
| Art Unit(s) | 3723, 3727, 3203, 2899 |
| Total Applications | 3154 |
| Issued Applications | 2531 |
| Pending Applications | 105 |
| Abandoned Applications | 520 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 885685
[patent_doc_number] => 07352001
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-04-01
[patent_title] => 'Method of editing a semiconductor die'
[patent_app_type] => utility
[patent_app_number] => 11/451918
[patent_app_country] => US
[patent_app_date] => 2006-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2656
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/352/07352001.pdf
[firstpage_image] =>[orig_patent_app_number] => 11451918
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451918 | Method of editing a semiconductor die | Jun 11, 2006 | Issued |
Array
(
[id] => 5602403
[patent_doc_number] => 20060292748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-28
[patent_title] => 'Package having bond-sealed underbump'
[patent_app_type] => utility
[patent_app_number] => 11/447764
[patent_app_country] => US
[patent_app_date] => 2006-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7065
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0292/20060292748.pdf
[firstpage_image] =>[orig_patent_app_number] => 11447764
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/447764 | Package having bond-sealed underbump | Jun 5, 2006 | Issued |
Array
(
[id] => 6264022
[patent_doc_number] => 20100252843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'LIGHT-EMITTING ELEMENT MOUNTING SUBSTRATE, LIGHT-EMITTING ELEMENT PACKAGE, DISPLAY DEVICE, AND ILLUMINATION DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/303022
[patent_app_country] => US
[patent_app_date] => 2006-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5113
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20100252843.pdf
[firstpage_image] =>[orig_patent_app_number] => 12303022
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/303022 | Light-emitting element mounting substrate, light-emitting element package, display device, and illumination device | May 30, 2006 | Issued |
Array
(
[id] => 586180
[patent_doc_number] => 07449769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Superconducting system, superconducting circuit chip, and high-temperature superconducting junction device with a shunt resistor'
[patent_app_type] => utility
[patent_app_number] => 11/442427
[patent_app_country] => US
[patent_app_date] => 2006-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 11842
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/449/07449769.pdf
[firstpage_image] =>[orig_patent_app_number] => 11442427
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/442427 | Superconducting system, superconducting circuit chip, and high-temperature superconducting junction device with a shunt resistor | May 29, 2006 | Issued |
Array
(
[id] => 4487654
[patent_doc_number] => 07902654
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'System and method of silicon switched power delivery using a package'
[patent_app_type] => utility
[patent_app_number] => 11/431790
[patent_app_country] => US
[patent_app_date] => 2006-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10314
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/902/07902654.pdf
[firstpage_image] =>[orig_patent_app_number] => 11431790
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/431790 | System and method of silicon switched power delivery using a package | May 9, 2006 | Issued |
Array
(
[id] => 386977
[patent_doc_number] => 07304346
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-04
[patent_title] => 'Flash memory cell transistor and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/430118
[patent_app_country] => US
[patent_app_date] => 2006-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 3063
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/304/07304346.pdf
[firstpage_image] =>[orig_patent_app_number] => 11430118
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/430118 | Flash memory cell transistor and method for fabricating the same | May 8, 2006 | Issued |
Array
(
[id] => 4462222
[patent_doc_number] => 07880189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Dislocation-based light emitter'
[patent_app_type] => utility
[patent_app_number] => 11/919915
[patent_app_country] => US
[patent_app_date] => 2006-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6296
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/880/07880189.pdf
[firstpage_image] =>[orig_patent_app_number] => 11919915
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/919915 | Dislocation-based light emitter | May 2, 2006 | Issued |
Array
(
[id] => 585940
[patent_doc_number] => 07449741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'SRAM cell structure and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/416699
[patent_app_country] => US
[patent_app_date] => 2006-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 7512
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/449/07449741.pdf
[firstpage_image] =>[orig_patent_app_number] => 11416699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/416699 | SRAM cell structure and manufacturing method thereof | May 1, 2006 | Issued |
Array
(
[id] => 5780153
[patent_doc_number] => 20060202248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-14
[patent_title] => 'SRAM cell structure and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/416926
[patent_app_country] => US
[patent_app_date] => 2006-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7504
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20060202248.pdf
[firstpage_image] =>[orig_patent_app_number] => 11416926
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/416926 | SRAM cell structure and manufacturing method thereof | May 1, 2006 | Issued |
Array
(
[id] => 380314
[patent_doc_number] => 07309890
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-18
[patent_title] => 'SRAM cell structure and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/416925
[patent_app_country] => US
[patent_app_date] => 2006-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 7507
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/309/07309890.pdf
[firstpage_image] =>[orig_patent_app_number] => 11416925
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/416925 | SRAM cell structure and manufacturing method thereof | May 1, 2006 | Issued |
Array
(
[id] => 5757367
[patent_doc_number] => 20060208312
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-21
[patent_title] => 'Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card'
[patent_app_type] => utility
[patent_app_number] => 11/414226
[patent_app_country] => US
[patent_app_date] => 2006-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 70384
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0208/20060208312.pdf
[firstpage_image] =>[orig_patent_app_number] => 11414226
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/414226 | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card | Apr 30, 2006 | Issued |
Array
(
[id] => 885669
[patent_doc_number] => 07351991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-01
[patent_title] => 'Methods for forming phase-change memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/413318
[patent_app_country] => US
[patent_app_date] => 2006-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 7776
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/351/07351991.pdf
[firstpage_image] =>[orig_patent_app_number] => 11413318
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/413318 | Methods for forming phase-change memory devices | Apr 27, 2006 | Issued |
Array
(
[id] => 334613
[patent_doc_number] => 07508025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-24
[patent_title] => 'Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators'
[patent_app_type] => utility
[patent_app_number] => 11/380599
[patent_app_country] => US
[patent_app_date] => 2006-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 10591
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/508/07508025.pdf
[firstpage_image] =>[orig_patent_app_number] => 11380599
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/380599 | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators | Apr 26, 2006 | Issued |
Array
(
[id] => 7601447
[patent_doc_number] => 07385257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-10
[patent_title] => 'Hybrid orientation SOI substrates, and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/411280
[patent_app_country] => US
[patent_app_date] => 2006-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5274
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/385/07385257.pdf
[firstpage_image] =>[orig_patent_app_number] => 11411280
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/411280 | Hybrid orientation SOI substrates, and method for forming the same | Apr 25, 2006 | Issued |
Array
(
[id] => 5832173
[patent_doc_number] => 20060244003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Nitride semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/410920
[patent_app_country] => US
[patent_app_date] => 2006-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7508
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0244/20060244003.pdf
[firstpage_image] =>[orig_patent_app_number] => 11410920
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/410920 | Nitride semiconductor device | Apr 25, 2006 | Issued |
Array
(
[id] => 5208219
[patent_doc_number] => 20070246803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-25
[patent_title] => 'Semiconductor constructions, and methods of forming semiconductor constructions'
[patent_app_type] => utility
[patent_app_number] => 11/411490
[patent_app_country] => US
[patent_app_date] => 2006-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 4960
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20070246803.pdf
[firstpage_image] =>[orig_patent_app_number] => 11411490
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/411490 | Methods of forming semiconductor constructions | Apr 24, 2006 | Issued |
Array
(
[id] => 5327774
[patent_doc_number] => 20090108251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'CONTROLLED GROWTH OF A NANOSTRUCTURE ON A SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/412060
[patent_app_country] => US
[patent_app_date] => 2006-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 26945
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20090108251.pdf
[firstpage_image] =>[orig_patent_app_number] => 11412060
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/412060 | Controlled growth of a nanostructure on a substrate | Apr 24, 2006 | Issued |
Array
(
[id] => 5916348
[patent_doc_number] => 20060237726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-26
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/409040
[patent_app_country] => US
[patent_app_date] => 2006-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 12998
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20060237726.pdf
[firstpage_image] =>[orig_patent_app_number] => 11409040
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/409040 | Semiconductor device | Apr 23, 2006 | Issued |
Array
(
[id] => 5208157
[patent_doc_number] => 20070246741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-25
[patent_title] => 'Stress relaxation for top of transistor gate'
[patent_app_type] => utility
[patent_app_number] => 11/409090
[patent_app_country] => US
[patent_app_date] => 2006-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1469
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20070246741.pdf
[firstpage_image] =>[orig_patent_app_number] => 11409090
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/409090 | Stress relaxation for top of transistor gate | Apr 23, 2006 | Issued |
Array
(
[id] => 5512090
[patent_doc_number] => 20090212394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/912606
[patent_app_country] => US
[patent_app_date] => 2006-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3357
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20090212394.pdf
[firstpage_image] =>[orig_patent_app_number] => 11912606
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/912606 | BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME | Apr 20, 2006 | Abandoned |