
Robert A. Rose
Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )
| Most Active Art Unit | 3723 |
| Art Unit(s) | 3723, 3727, 3203, 2899 |
| Total Applications | 3154 |
| Issued Applications | 2531 |
| Pending Applications | 105 |
| Abandoned Applications | 520 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 377397
[patent_doc_number] => 07312498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-25
[patent_title] => 'Nonvolatile semiconductor memory cell and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/331228
[patent_app_country] => US
[patent_app_date] => 2006-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 21
[patent_no_of_words] => 6122
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/312/07312498.pdf
[firstpage_image] =>[orig_patent_app_number] => 11331228
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/331228 | Nonvolatile semiconductor memory cell and method of manufacturing the same | Jan 12, 2006 | Issued |
Array
(
[id] => 440110
[patent_doc_number] => 07259395
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-21
[patent_title] => 'Dual panel type organic electroluminescent display device and manufacturing method for the same'
[patent_app_type] => utility
[patent_app_number] => 11/324265
[patent_app_country] => US
[patent_app_date] => 2006-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[pdf_file] => patents/07/259/07259395.pdf
[firstpage_image] =>[orig_patent_app_number] => 11324265
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/324265 | Dual panel type organic electroluminescent display device and manufacturing method for the same | Jan 3, 2006 | Issued |
Array
(
[id] => 425467
[patent_doc_number] => 07271450
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-18
[patent_title] => 'Dual-gate structure and method of fabricating integrated circuits having dual-gate structures'
[patent_app_type] => utility
[patent_app_number] => 11/303530
[patent_app_country] => US
[patent_app_date] => 2005-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/07/271/07271450.pdf
[firstpage_image] =>[orig_patent_app_number] => 11303530
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/303530 | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures | Dec 15, 2005 | Issued |
Array
(
[id] => 5116942
[patent_doc_number] => 20070138656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Providing a metal layer in a semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 11/300720
[patent_app_country] => US
[patent_app_date] => 2005-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2307
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[firstpage_image] =>[orig_patent_app_number] => 11300720
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/300720 | Providing a metal layer in a semiconductor package | Dec 14, 2005 | Issued |
Array
(
[id] => 5116930
[patent_doc_number] => 20070138644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Structure and method of making capped chip having discrete article assembled into vertical interconnect'
[patent_app_type] => utility
[patent_app_number] => 11/300900
[patent_app_country] => US
[patent_app_date] => 2005-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 16331
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[pdf_file] => publications/A1/0138/20070138644.pdf
[firstpage_image] =>[orig_patent_app_number] => 11300900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/300900 | Structure and method of making capped chip having discrete article assembled into vertical interconnect | Dec 14, 2005 | Abandoned |
Array
(
[id] => 6294970
[patent_doc_number] => 20100065885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-18
[patent_title] => 'SOI DEVICE WITH MORE IMMUNITY FROM STUBSTRATE VOLTAGE'
[patent_app_type] => utility
[patent_app_number] => 11/813018
[patent_app_country] => US
[patent_app_date] => 2005-12-15
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11813018
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/813018 | SOI device with more immunity from substrate voltage | Dec 14, 2005 | Issued |
Array
(
[id] => 5908776
[patent_doc_number] => 20060124928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Integrated circuit disabling'
[patent_app_type] => utility
[patent_app_number] => 11/302620
[patent_app_country] => US
[patent_app_date] => 2005-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
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[pdf_file] => publications/A1/0124/20060124928.pdf
[firstpage_image] =>[orig_patent_app_number] => 11302620
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/302620 | Integrated circuit disabling | Dec 13, 2005 | Abandoned |
Array
(
[id] => 5911361
[patent_doc_number] => 20060126423
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Memory element and memory device'
[patent_app_type] => utility
[patent_app_number] => 11/302781
[patent_app_country] => US
[patent_app_date] => 2005-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 9154
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[pdf_file] => publications/A1/0126/20060126423.pdf
[firstpage_image] =>[orig_patent_app_number] => 11302781
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/302781 | Memory element and memory device | Dec 13, 2005 | Issued |
Array
(
[id] => 904338
[patent_doc_number] => 07335955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-26
[patent_title] => 'ESD protection for passive integrated devices'
[patent_app_type] => utility
[patent_app_number] => 11/300710
[patent_app_country] => US
[patent_app_date] => 2005-12-14
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[pdf_file] => patents/07/335/07335955.pdf
[firstpage_image] =>[orig_patent_app_number] => 11300710
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/300710 | ESD protection for passive integrated devices | Dec 13, 2005 | Issued |
Array
(
[id] => 349172
[patent_doc_number] => 07495290
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-24
[patent_title] => 'Semiconductor devices and methods of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 11/300050
[patent_app_country] => US
[patent_app_date] => 2005-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/07/495/07495290.pdf
[firstpage_image] =>[orig_patent_app_number] => 11300050
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/300050 | Semiconductor devices and methods of manufacture thereof | Dec 13, 2005 | Issued |
Array
(
[id] => 5805200
[patent_doc_number] => 20060091553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Wiring board and method for producing same'
[patent_app_type] => utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/302582 | Wiring board and method for producing same | Dec 12, 2005 | Abandoned |
Array
(
[id] => 844073
[patent_doc_number] => 07388270
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[patent_kind] => B2
[patent_issue_date] => 2008-06-17
[patent_title] => 'Method of fabricating CMOS image sensor'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/301830 | Method of fabricating CMOS image sensor | Dec 11, 2005 | Issued |
Array
(
[id] => 5250635
[patent_doc_number] => 20070132091
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[patent_issue_date] => 2007-06-14
[patent_title] => 'Thermal enhanced upper and dual heat sink exposed molded leadless package'
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Array
(
[id] => 5690606
[patent_doc_number] => 20060150751
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[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'Power semiconductor module'
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Array
(
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[patent_title] => 'Surface emitting type device, and method for manufacturing the same'
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Array
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Array
(
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[patent_title] => 'Semiconductor device, carrier, card reader, methods of initializing and checking authenticity'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/294280 | Non-volatile memory array structure | Dec 4, 2005 | Issued |