Robert A. Rose

Array ( [id] => 7198047 [patent_doc_number] => 20050051763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Nanophase multilayer barrier and process' [patent_app_type] => utility [patent_app_number] => 10/934530 [patent_app_country] => US [patent_app_date] => 2004-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8483 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051763.pdf [firstpage_image] =>[orig_patent_app_number] => 10934530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7126248 [patent_doc_number] => 20050057992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Magnetoresistance effect element, method of manufacture thereof, magnetic storage and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 10/933418 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6855 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057992.pdf [firstpage_image] =>[orig_patent_app_number] => 10933418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6916900 [patent_doc_number] => 20050094461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Integrated semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/932888 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094461.pdf [firstpage_image] =>[orig_patent_app_number] => 10932888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5898377 [patent_doc_number] => 20060043610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Power controller with bond wire fuse' [patent_app_type] => utility [patent_app_number] => 10/931950 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1744 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043610.pdf [firstpage_image] =>[orig_patent_app_number] => 10931950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 668923 [patent_doc_number] => 07095122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same' [patent_app_type] => utility [patent_app_number] => 10/932840 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4912 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095122.pdf [firstpage_image] =>[orig_patent_app_number] => 10932840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5898216 [patent_doc_number] => 20060043449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors' [patent_app_type] => utility [patent_app_number] => 10/932150 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6331 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043449.pdf [firstpage_image] =>[orig_patent_app_number] => 10932150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 664110 [patent_doc_number] => 07102205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Bipolar transistor with extrinsic stress layer' [patent_app_type] => utility [patent_app_number] => 10/931660 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5373 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102205.pdf [firstpage_image] =>[orig_patent_app_number] => 10931660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 503234 [patent_doc_number] => 07205638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Silicon building blocks in integrated circuit packaging' [patent_app_type] => utility [patent_app_number] => 10/931497 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205638.pdf [firstpage_image] =>[orig_patent_app_number] => 10931497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 634564 [patent_doc_number] => 07129567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements' [patent_app_type] => utility [patent_app_number] => 10/931959 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 48 [patent_no_of_words] => 15568 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129567.pdf [firstpage_image] =>[orig_patent_app_number] => 10931959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 961319 [patent_doc_number] => 06952032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Programmable array logic or memory devices with asymmetrical tunnel barriers' [patent_app_type] => utility [patent_app_number] => 10/931540 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 14355 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952032.pdf [firstpage_image] =>[orig_patent_app_number] => 10931540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 738904 [patent_doc_number] => 07034372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'HGA dynamics testing with shear mode piezo transducers' [patent_app_type] => utility [patent_app_number] => 10/930918 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2766 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034372.pdf [firstpage_image] =>[orig_patent_app_number] => 10930918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 703163 [patent_doc_number] => 07064430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Stacked die packaging and fabrication method' [patent_app_type] => utility [patent_app_number] => 10/931919 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5266 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064430.pdf [firstpage_image] =>[orig_patent_app_number] => 10931919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7147772 [patent_doc_number] => 20050023603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators' [patent_app_type] => utility [patent_app_number] => 10/929986 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10639 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023603.pdf [firstpage_image] =>[orig_patent_app_number] => 10929986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7147770 [patent_doc_number] => 20050023602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers' [patent_app_type] => utility [patent_app_number] => 10/929916 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14523 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023602.pdf [firstpage_image] =>[orig_patent_app_number] => 10929916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619736 [patent_doc_number] => 06943450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Packaged microelectronic devices and methods of forming same' [patent_app_type] => utility [patent_app_number] => 10/929613 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6485 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943450.pdf [firstpage_image] =>[orig_patent_app_number] => 10929613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7148001 [patent_doc_number] => 20050023676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Solder pads and method of making a solder pad' [patent_app_type] => utility [patent_app_number] => 10/925410 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3993 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023676.pdf [firstpage_image] =>[orig_patent_app_number] => 10925410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 752014 [patent_doc_number] => 07023099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Wafer cleaning method and resulting wafer' [patent_app_type] => utility [patent_app_number] => 10/927612 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5193 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023099.pdf [firstpage_image] =>[orig_patent_app_number] => 10927612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 484270 [patent_doc_number] => 07220989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Test apparatus for a semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/921188 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220989.pdf [firstpage_image] =>[orig_patent_app_number] => 10921188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 946829 [patent_doc_number] => 06965163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Substrate-less microelectronic package' [patent_app_type] => utility [patent_app_number] => 10/916022 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2573 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965163.pdf [firstpage_image] =>[orig_patent_app_number] => 10916022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 702950 [patent_doc_number] => 07064351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Circuit array substrate' [patent_app_type] => utility [patent_app_number] => 10/911600 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4457 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064351.pdf [firstpage_image] =>[orig_patent_app_number] => 10911600 [rel_patent_id] =>[rel_patent_doc_number] =>)