
Robert A. Rose
Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )
| Most Active Art Unit | 3723 |
| Art Unit(s) | 3723, 3727, 3203, 2899 |
| Total Applications | 3154 |
| Issued Applications | 2531 |
| Pending Applications | 105 |
| Abandoned Applications | 520 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7183515
[patent_doc_number] => 20050161820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'Integrated circuit with conductive grid for power distribution'
[patent_app_type] => utility
[patent_app_number] => 10/765810
[patent_app_country] => US
[patent_app_date] => 2004-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2912
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20050161820.pdf
[firstpage_image] =>[orig_patent_app_number] => 10765810
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/765810 | Integrated circuit with conductive grid for power distribution | Jan 26, 2004 | Abandoned |
Array
(
[id] => 7677547
[patent_doc_number] => 20040152279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Semiconductor latches and SRAM devices'
[patent_app_type] => new
[patent_app_number] => 10/764048
[patent_app_country] => US
[patent_app_date] => 2004-01-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0152/20040152279.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764048 | Semiconductor latches and SRAM devices | Jan 25, 2004 | Issued |
Array
(
[id] => 7414704
[patent_doc_number] => 20040159869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-19
[patent_title] => 'Memory array with high temperature wiring'
[patent_app_type] => new
[patent_app_number] => 10/765406
[patent_app_country] => US
[patent_app_date] => 2004-01-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/765406 | Memory array with high temperature wiring | Jan 25, 2004 | Issued |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2004-08-19
[patent_title] => 'Semiconductor device and method for designing the same'
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[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 10761310
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/761310 | Semiconductor device and method for designing the same | Jan 21, 2004 | Issued |
Array
(
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[patent_title] => 'Semiconductor devices with scalable two transistor memory cells and methods of fabricating the same'
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[firstpage_image] =>[orig_patent_app_number] => 10763016
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Array
(
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[patent_doc_number] => 06825526
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[patent_issue_date] => 2004-11-30
[patent_title] => 'Structure for increasing drive current in a memory array and related method'
[patent_app_type] => B1
[patent_app_number] => 10/759809
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/759809 | Structure for increasing drive current in a memory array and related method | Jan 15, 2004 | Issued |
Array
(
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[patent_title] => 'Method for manufacturing a semiconductor device'
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[pdf_file] => publications/A1/0232/20040232453.pdf
[firstpage_image] =>[orig_patent_app_number] => 10759609
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/759609 | Method for manufacturing a semiconductor device | Jan 15, 2004 | Issued |
Array
(
[id] => 6981173
[patent_doc_number] => 20050151241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'MULTILAYER CERAMIC SUBSTRATE WITH SINGLE VIA ANCHORED PAD AND METHOD OF FORMING'
[patent_app_type] => utility
[patent_app_number] => 10/707810
[patent_app_country] => US
[patent_app_date] => 2004-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0151/20050151241.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707810
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707810 | Multilayer ceramic substrate with single via anchored pad and method of forming | Jan 13, 2004 | Issued |
Array
(
[id] => 7420773
[patent_doc_number] => 20040183110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'MAGNETIC MEMORY UNIT AND MAGNETIC MEMORY ARRAY'
[patent_app_type] => new
[patent_app_number] => 10/754910
[patent_app_country] => US
[patent_app_date] => 2004-01-09
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[firstpage_image] =>[orig_patent_app_number] => 10754910
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/754910 | Magnetic memory unit and magnetic memory array | Jan 8, 2004 | Issued |
Array
(
[id] => 1005902
[patent_doc_number] => 06906349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Polysilicon thin film transistor array panel and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/752510
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[firstpage_image] =>[orig_patent_app_number] => 10752510
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/752510 | Polysilicon thin film transistor array panel and manufacturing method thereof | Jan 7, 2004 | Issued |
Array
(
[id] => 7612400
[patent_doc_number] => 06903437
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-06-07
[patent_title] => 'Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods'
[patent_app_type] => utility
[patent_app_number] => 10/753914
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[pdf_file] => patents/06/903/06903437.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/753914 | Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods | Jan 6, 2004 | Issued |
Array
(
[id] => 7309228
[patent_doc_number] => 20040142526
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[patent_title] => 'Fuse boxes with guard rings for integrated circuits and integrated circuits including the same'
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Array
(
[id] => 7616724
[patent_doc_number] => 06946718
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[patent_title] => 'Integrated fuse for multilayered structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/751710 | Integrated fuse for multilayered structure | Jan 4, 2004 | Issued |
Array
(
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[patent_title] => 'System and method for high performance heat sink for multiple chip devices'
[patent_app_type] => utility
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/743814 | Ferroelectric capacitor, process for production thereof and semiconductor device using the same | Dec 23, 2003 | Issued |
Array
(
[id] => 770100
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[patent_issue_date] => 2006-02-28
[patent_title] => 'Dual panel type organic electroluminescent display device and manufacturing method for the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/743010 | Dual panel type organic electroluminescent display device and manufacturing method for the same | Dec 22, 2003 | Issued |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/744412 | High-voltage bidirectional switch | Dec 22, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746908 | Metallic photonic box and its fabrication techniques | Dec 22, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/735710 | Semiconductor device and method of manufacturing the same | Dec 15, 2003 | Issued |