Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7288919 [patent_doc_number] => 20040110013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Method of increasing mechanical properties of semiconductor substrates' [patent_app_type] => new [patent_app_number] => 10/703803 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110013.pdf [firstpage_image] =>[orig_patent_app_number] => 10703803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703803
Method of increasing mechanical properties of semiconductor substrates Nov 6, 2003 Abandoned
Array ( [id] => 6915496 [patent_doc_number] => 20050093057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Common spacer dual gate memory cell and method for forming a nonvolatile memory array' [patent_app_type] => utility [patent_app_number] => 10/698514 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4533 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093057.pdf [firstpage_image] =>[orig_patent_app_number] => 10698514 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/698514
Common spacer dual gate memory cell and method for forming a nonvolatile memory array Nov 2, 2003 Abandoned
Array ( [id] => 1081412 [patent_doc_number] => 06836021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/698410 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836021.pdf [firstpage_image] =>[orig_patent_app_number] => 10698410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/698410
Semiconductor device Nov 2, 2003 Issued
Array ( [id] => 6915449 [patent_doc_number] => 20050093010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'IC PACKAGE WITH STACKED SHEET METAL SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 10/697610 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1447 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093010.pdf [firstpage_image] =>[orig_patent_app_number] => 10697610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697610
IC package with stacked sheet metal substrate Oct 30, 2003 Issued
Array ( [id] => 1056847 [patent_doc_number] => 06855984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Process to reduce gate edge drain leakage in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/697510 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4455 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855984.pdf [firstpage_image] =>[orig_patent_app_number] => 10697510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697510
Process to reduce gate edge drain leakage in semiconductor devices Oct 29, 2003 Issued
Array ( [id] => 712251 [patent_doc_number] => 07057258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Resistive memory device and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/695710 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3304 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057258.pdf [firstpage_image] =>[orig_patent_app_number] => 10695710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695710
Resistive memory device and method for making the same Oct 28, 2003 Issued
Array ( [id] => 7058889 [patent_doc_number] => 20050001248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Pinned photodiode structure and method of formation' [patent_app_type] => utility [patent_app_number] => 10/695160 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19751 [patent_no_of_claims] => 240 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001248.pdf [firstpage_image] =>[orig_patent_app_number] => 10695160 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695160
Pinned photodiode structure and method of formation Oct 28, 2003 Issued
Array ( [id] => 7414689 [patent_doc_number] => 20040159867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'MULTI-LAYER CONDUCTIVE MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 10/605757 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8243 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159867.pdf [firstpage_image] =>[orig_patent_app_number] => 10605757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605757
Multi-layer conductive memory device Oct 22, 2003 Issued
Array ( [id] => 7154297 [patent_doc_number] => 20050082559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Mask and method for using the mask in lithographic processing' [patent_app_type] => utility [patent_app_number] => 10/685004 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082559.pdf [firstpage_image] =>[orig_patent_app_number] => 10685004 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/685004
Mask and method for using the mask in lithographic processing Oct 14, 2003 Issued
Array ( [id] => 7159371 [patent_doc_number] => 20040075114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Low leakage schottky diode' [patent_app_type] => new [patent_app_number] => 10/684910 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2145 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075114.pdf [firstpage_image] =>[orig_patent_app_number] => 10684910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684910
Low leakage schottky diode Oct 13, 2003 Issued
Array ( [id] => 1086545 [patent_doc_number] => 06831359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Power semiconductor module' [patent_app_type] => B2 [patent_app_number] => 10/684310 [patent_app_country] => US [patent_app_date] => 2003-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4949 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831359.pdf [firstpage_image] =>[orig_patent_app_number] => 10684310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684310
Power semiconductor module Oct 10, 2003 Issued
Array ( [id] => 7295997 [patent_doc_number] => 20040124536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/682110 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4547 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124536.pdf [firstpage_image] =>[orig_patent_app_number] => 10682110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682110
Semiconductor device Oct 9, 2003 Abandoned
Array ( [id] => 700157 [patent_doc_number] => 07067862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Conductive memory device with conductive oxide electrodes' [patent_app_type] => utility [patent_app_number] => 10/682277 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 8189 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067862.pdf [firstpage_image] =>[orig_patent_app_number] => 10682277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682277
Conductive memory device with conductive oxide electrodes Oct 7, 2003 Issued
Array ( [id] => 7619751 [patent_doc_number] => 06943434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method for maintaining solder thickness in flipchip attach packaging processes' [patent_app_type] => utility [patent_app_number] => 10/678010 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4942 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943434.pdf [firstpage_image] =>[orig_patent_app_number] => 10678010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/678010
Method for maintaining solder thickness in flipchip attach packaging processes Oct 1, 2003 Issued
Array ( [id] => 7279724 [patent_doc_number] => 20040062101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Semiconductor memory device and method for arranging memory cells' [patent_app_type] => new [patent_app_number] => 10/674612 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5727 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20040062101.pdf [firstpage_image] =>[orig_patent_app_number] => 10674612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674612
Semiconductor memory device and method for arranging memory cells Sep 29, 2003 Issued
Array ( [id] => 7279720 [patent_doc_number] => 20040062097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Magnetic recording medium and magnetic memory apparatus' [patent_app_type] => new [patent_app_number] => 10/670216 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5250 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20040062097.pdf [firstpage_image] =>[orig_patent_app_number] => 10670216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670216
Magnetic recording medium and magnetic memory apparatus Sep 25, 2003 Issued
Array ( [id] => 1106222 [patent_doc_number] => 06812538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'MRAM cells having magnetic write lines with a stable magnetic state at the end regions' [patent_app_type] => B2 [patent_app_number] => 10/669216 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5085 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812538.pdf [firstpage_image] =>[orig_patent_app_number] => 10669216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/669216
MRAM cells having magnetic write lines with a stable magnetic state at the end regions Sep 22, 2003 Issued
Array ( [id] => 7267756 [patent_doc_number] => 20040056274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/665210 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6659 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20040056274.pdf [firstpage_image] =>[orig_patent_app_number] => 10665210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665210
Bipolar transistor Sep 21, 2003 Issued
Array ( [id] => 1069177 [patent_doc_number] => 06844591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Method of forming DRAM access transistors' [patent_app_type] => utility [patent_app_number] => 10/663710 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5168 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844591.pdf [firstpage_image] =>[orig_patent_app_number] => 10663710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663710
Method of forming DRAM access transistors Sep 16, 2003 Issued
Array ( [id] => 7626583 [patent_doc_number] => 06768179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'CMOS of semiconductor device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/663910 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3837 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768179.pdf [firstpage_image] =>[orig_patent_app_number] => 10663910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663910
CMOS of semiconductor device and method for manufacturing the same Sep 16, 2003 Issued
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