Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18983602 [patent_doc_number] => 11908791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Partial subtractive supervia enabling hyper-scaling [patent_app_type] => utility [patent_app_number] => 17/532310 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6314 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532310
Partial subtractive supervia enabling hyper-scaling Nov 21, 2021 Issued
Array ( [id] => 19223673 [patent_doc_number] => 20240188377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => LIGHT-EMITTING PANEL AND LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/287692 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18287692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/287692
LIGHT-EMITTING PANEL AND LIGHT-EMITTING DEVICE Nov 18, 2021 Pending
Array ( [id] => 18364370 [patent_doc_number] => 20230145961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MASKLESS ALIGNMENT SCHEME FOR BEOL MEMORY ARRAY MANUFACTURING [patent_app_type] => utility [patent_app_number] => 17/523086 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523086
Maskless alignment scheme for BEOL memory array manufacturing Nov 9, 2021 Issued
Array ( [id] => 18743488 [patent_doc_number] => 20230352476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/616677 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17616677 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/616677
Nitride-based semiconductor device and method for manufacturing the same Oct 26, 2021 Issued
Array ( [id] => 19812363 [patent_doc_number] => 12243776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings [patent_app_type] => utility [patent_app_number] => 17/508036 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 129 [patent_no_of_words] => 44286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508036
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings Oct 21, 2021 Issued
Array ( [id] => 17403075 [patent_doc_number] => 20220045166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/508197 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508197
Semiconductor device and method for fabricating the same Oct 21, 2021 Issued
Array ( [id] => 18757572 [patent_doc_number] => 20230361035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/245746 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245746 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245746
SEMICONDUCTOR DEVICE Oct 18, 2021 Pending
Array ( [id] => 18325244 [patent_doc_number] => 20230123372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => INTERCONNECT INCLUDING INTEGRALLY FORMED CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/451254 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451254
Interconnect including integrally formed capacitor Oct 17, 2021 Issued
Array ( [id] => 18804383 [patent_doc_number] => 11837547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => PIC die with optical deflector for ambient light [patent_app_type] => utility [patent_app_number] => 17/450324 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450324
PIC die with optical deflector for ambient light Oct 7, 2021 Issued
Array ( [id] => 17708780 [patent_doc_number] => 20220208788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS [patent_app_type] => utility [patent_app_number] => 17/494114 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494114
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings Oct 4, 2021 Issued
Array ( [id] => 17509385 [patent_doc_number] => 20220102488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DIELECTRIC AND ISOLATION LOWER FIN MATERIAL FOR FIN-BASED ELECTRONICS [patent_app_type] => utility [patent_app_number] => 17/493213 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493213
Dielectric and isolation lower fin material for fin-based electronics Oct 3, 2021 Issued
Array ( [id] => 18285635 [patent_doc_number] => 20230101107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SIMULTANEOUS FILLING OF VARIABLE ASPECT RATIO SINGLE DAMASCENE CONTACT TO GATE AND TRENCH VIAS WITH LOW RESISTANCE BARRIERLESS SELECTIVE METALLIZATION [patent_app_type] => utility [patent_app_number] => 17/485299 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485299
Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization Sep 23, 2021 Issued
Array ( [id] => 18284896 [patent_doc_number] => 20230100368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => DUAL COLOR VIA PATTERNING [patent_app_type] => utility [patent_app_number] => 17/483922 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483922
Dual color via patterning Sep 23, 2021 Issued
Array ( [id] => 19720354 [patent_doc_number] => 12205897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells [patent_app_type] => utility [patent_app_number] => 17/483672 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483672
Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells Sep 22, 2021 Issued
Array ( [id] => 18999158 [patent_doc_number] => 11916014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Gate contact inside gate cut trench [patent_app_type] => utility [patent_app_number] => 17/482874 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482874
Gate contact inside gate cut trench Sep 22, 2021 Issued
Array ( [id] => 17339432 [patent_doc_number] => 20220005763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/480615 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480615
Semiconductor device Sep 20, 2021 Issued
Array ( [id] => 18295350 [patent_doc_number] => 20230105036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/478105 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478105
Semiconductor device and method forming the same Sep 16, 2021 Issued
Array ( [id] => 19095492 [patent_doc_number] => 11956975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => BEOL fat wire level ground rule compatible embedded artificial intelligence integration [patent_app_type] => utility [patent_app_number] => 17/477039 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 57 [patent_no_of_words] => 14723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477039
BEOL fat wire level ground rule compatible embedded artificial intelligence integration Sep 15, 2021 Issued
Array ( [id] => 20405609 [patent_doc_number] => 12495599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Nitride-based semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/598909 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17598909 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/598909
Nitride-based semiconductor device and method for manufacturing the same Sep 14, 2021 Issued
Array ( [id] => 18653316 [patent_doc_number] => 20230299156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => COMPOUND SEMICONDUCTOR DEVICES COMBINED IN A FACE-TO-FACE ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 18/245451 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245451 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245451
COMPOUND SEMICONDUCTOR DEVICES COMBINED IN A FACE-TO-FACE ARRANGEMENT Sep 13, 2021 Pending
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