
Robert A. Rose
Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )
| Most Active Art Unit | 3723 |
| Art Unit(s) | 3723, 3727, 3203, 2899 |
| Total Applications | 3154 |
| Issued Applications | 2531 |
| Pending Applications | 105 |
| Abandoned Applications | 520 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17886546
[patent_doc_number] => 20220302024
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR DEVICE, TEMPLATE, AND METHOD OF MANUFACTURING TEMPLATE
[patent_app_type] => utility
[patent_app_number] => 17/470529
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13606
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470529
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/470529 | Semiconductor device, template, and method of manufacturing template | Sep 8, 2021 | Issued |
Array
(
[id] => 17319444
[patent_doc_number] => 20210408494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => METHODS OF OLED DISPLAY FABRICATION SUITED FOR DEPOSITION OF LIGHT ENHANCING LAYER
[patent_app_type] => utility
[patent_app_number] => 17/471074
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6951
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471074
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/471074 | METHODS OF OLED DISPLAY FABRICATION SUITED FOR DEPOSITION OF LIGHT ENHANCING LAYER | Sep 8, 2021 | Abandoned |
Array
(
[id] => 20229322
[patent_doc_number] => 12417978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Microelectronic assemblies having backside die-to-package interconnects
[patent_app_type] => utility
[patent_app_number] => 17/470189
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 36
[patent_no_of_words] => 11893
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470189
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/470189 | Microelectronic assemblies having backside die-to-package interconnects | Sep 8, 2021 | Issued |
Array
(
[id] => 18840186
[patent_doc_number] => 11848266
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Three-dimensional semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/467678
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 29
[patent_no_of_words] => 6628
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467678
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/467678 | Three-dimensional semiconductor device | Sep 6, 2021 | Issued |
Array
(
[id] => 19291548
[patent_doc_number] => 12030894
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Composition for organic optoelectronic device, organic optoelectronic device and display device
[patent_app_type] => utility
[patent_app_number] => 17/466504
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 7411
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 431
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466504
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/466504 | Composition for organic optoelectronic device, organic optoelectronic device and display device | Sep 2, 2021 | Issued |
Array
(
[id] => 19200657
[patent_doc_number] => 11997921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-28
[patent_title] => Organic light emitting device
[patent_app_type] => utility
[patent_app_number] => 17/466121
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 23016
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 560
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466121
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/466121 | Organic light emitting device | Sep 2, 2021 | Issued |
Array
(
[id] => 17300521
[patent_doc_number] => 20210396360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-23
[patent_title] => NANO-SCALE LIGHT-EMITTING DIODE (LED) ELECTRODE ASSEMBLY EMITTING POLARIZED LIGHT, METHOD OF MANUFACTURING THE SAME, AND POLARIZED LED LAMP HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/467163
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16145
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467163
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/467163 | Nano-scale light-emitting diode (LED) electrode assembly emitting polarized light, method of manufacturing the same, and polarized LED lamp having the same | Sep 2, 2021 | Issued |
Array
(
[id] => 17886770
[patent_doc_number] => 20220302248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/466841
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466841
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/466841 | Semiconductor device | Sep 2, 2021 | Issued |
Array
(
[id] => 19016411
[patent_doc_number] => 11923355
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-05
[patent_title] => Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/461133
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 11335
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461133
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461133 | Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same | Aug 29, 2021 | Issued |
Array
(
[id] => 17295545
[patent_doc_number] => 20210391384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => MAGNETIC MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/460635
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460635
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460635 | Magnetic memory devices | Aug 29, 2021 | Issued |
Array
(
[id] => 19460222
[patent_doc_number] => 12100732
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-24
[patent_title] => Semiconductor device and method of manufacturing same
[patent_app_type] => utility
[patent_app_number] => 17/459703
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 16971
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459703
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459703 | Semiconductor device and method of manufacturing same | Aug 26, 2021 | Issued |
Array
(
[id] => 17660732
[patent_doc_number] => 20220181197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => BURIED POWER RAIL CONTACT FORMATION
[patent_app_type] => utility
[patent_app_number] => 17/459384
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4190
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459384
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459384 | Buried power rail contact formation | Aug 26, 2021 | Issued |
Array
(
[id] => 17692233
[patent_doc_number] => 20220199526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => INTEGRATED CIRCUIT DEVICES HAVING IMPROVED CONTACT PLUG STRUCTURES THEREIN
[patent_app_type] => utility
[patent_app_number] => 17/406887
[patent_app_country] => US
[patent_app_date] => 2021-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13519
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406887
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/406887 | Integrated circuit devices having improved contact plug structures therein | Aug 18, 2021 | Issued |
Array
(
[id] => 19079564
[patent_doc_number] => 11948944
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-02
[patent_title] => Optimized contact resistance for stacked FET devices
[patent_app_type] => utility
[patent_app_number] => 17/404628
[patent_app_country] => US
[patent_app_date] => 2021-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 30
[patent_no_of_words] => 8509
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404628
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/404628 | Optimized contact resistance for stacked FET devices | Aug 16, 2021 | Issued |
Array
(
[id] => 17833736
[patent_doc_number] => 20220271040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-25
[patent_title] => MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/399471
[patent_app_country] => US
[patent_app_date] => 2021-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8098
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399471
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/399471 | Memory cell and semiconductor memory device with the same | Aug 10, 2021 | Issued |
Array
(
[id] => 19223572
[patent_doc_number] => 20240188276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => METHOD FOR MANUFACTURING MEMORY DEVICE AND MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/782791
[patent_app_country] => US
[patent_app_date] => 2021-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7823
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782791
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/782791 | Method for manufacturing memory device and memory | Aug 5, 2021 | Issued |
Array
(
[id] => 18857474
[patent_doc_number] => 11855070
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor device, method of and system for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/390108
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 17288
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390108
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/390108 | Semiconductor device, method of and system for manufacturing semiconductor device | Jul 29, 2021 | Issued |
Array
(
[id] => 18167970
[patent_doc_number] => 20230034578
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => 3D DRAM WITH LAMINAR CELLS
[patent_app_type] => utility
[patent_app_number] => 17/389235
[patent_app_country] => US
[patent_app_date] => 2021-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10130
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389235
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/389235 | 3D DRAM WITH LAMINAR CELLS | Jul 28, 2021 | Abandoned |
Array
(
[id] => 18857378
[patent_doc_number] => 11854973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor device with reduced resistance and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/389141
[patent_app_country] => US
[patent_app_date] => 2021-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11339
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389141
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/389141 | Semiconductor device with reduced resistance and method for manufacturing the same | Jul 28, 2021 | Issued |
Array
(
[id] => 18061786
[patent_doc_number] => 20220392873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => MULTI-WAFER INTEGRATION
[patent_app_type] => utility
[patent_app_number] => 17/387731
[patent_app_country] => US
[patent_app_date] => 2021-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7408
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387731
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/387731 | Multi-wafer integration | Jul 27, 2021 | Issued |