
Robert A. Rose
Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )
| Most Active Art Unit | 3723 |
| Art Unit(s) | 3723, 3727, 3203, 2899 |
| Total Applications | 3154 |
| Issued Applications | 2531 |
| Pending Applications | 105 |
| Abandoned Applications | 520 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16731470
[patent_doc_number] => 20210098618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => Negative Capacitance Transistor with a Diffusion Blocking Layer
[patent_app_type] => utility
[patent_app_number] => 17/113821
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6737
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113821
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/113821 | Negative capacitance transistor with a diffusion blocking layer | Dec 6, 2020 | Issued |
Array
(
[id] => 16723757
[patent_doc_number] => 20210090904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => 3D PRINTED SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/114240
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5388
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114240
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/114240 | 3D printed semiconductor package | Dec 6, 2020 | Issued |
Array
(
[id] => 18219678
[patent_doc_number] => 11594628
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors
[patent_app_type] => utility
[patent_app_number] => 17/111561
[patent_app_country] => US
[patent_app_date] => 2020-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 9484
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111561
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/111561 | Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors | Dec 3, 2020 | Issued |
Array
(
[id] => 17925958
[patent_doc_number] => 11469221
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Integrated circuit and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/108635
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 34
[patent_no_of_words] => 14054
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108635
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/108635 | Integrated circuit and manufacturing method thereof | Nov 30, 2020 | Issued |
Array
(
[id] => 19945473
[patent_doc_number] => 12317623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Imaging apparatus, manufacturing method thereof, and electronic equipment
[patent_app_type] => utility
[patent_app_number] => 17/756358
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 82
[patent_figures_cnt] => 128
[patent_no_of_words] => 27476
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756358
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/756358 | Imaging apparatus, manufacturing method thereof, and electronic equipment | Nov 30, 2020 | Issued |
Array
(
[id] => 18190620
[patent_doc_number] => 11581221
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Method and IC design with non-linear power rails
[patent_app_type] => utility
[patent_app_number] => 17/106639
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 30
[patent_no_of_words] => 6555
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106639
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/106639 | Method and IC design with non-linear power rails | Nov 29, 2020 | Issued |
Array
(
[id] => 17389486
[patent_doc_number] => 20220037338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-03
[patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/104179
[patent_app_country] => US
[patent_app_date] => 2020-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11546
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104179
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/104179 | Semiconductor structure and forming method thereof | Nov 24, 2020 | Issued |
Array
(
[id] => 17630643
[patent_doc_number] => 20220165658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-26
[patent_title] => HIGH VOLTAGE DECOUPLING CAPACITOR AND INTEGRATION METHODS
[patent_app_type] => utility
[patent_app_number] => 17/100950
[patent_app_country] => US
[patent_app_date] => 2020-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5962
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100950
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/100950 | High voltage decoupling capacitor and integration methods | Nov 22, 2020 | Issued |
Array
(
[id] => 17652700
[patent_doc_number] => 11355440
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-07
[patent_title] => Semiconductor package including interposer
[patent_app_type] => utility
[patent_app_number] => 17/100171
[patent_app_country] => US
[patent_app_date] => 2020-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 11286
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100171
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/100171 | Semiconductor package including interposer | Nov 19, 2020 | Issued |
Array
(
[id] => 17638134
[patent_doc_number] => 11348868
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-31
[patent_title] => Channel structure for signal transmission
[patent_app_type] => utility
[patent_app_number] => 16/950860
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2429
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950860
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950860 | Channel structure for signal transmission | Nov 16, 2020 | Issued |
Array
(
[id] => 18001065
[patent_doc_number] => 11502176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-15
[patent_title] => Semiconductor device with ferroelectric aluminum nitride
[patent_app_type] => utility
[patent_app_number] => 17/088461
[patent_app_country] => US
[patent_app_date] => 2020-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 6451
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088461
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/088461 | Semiconductor device with ferroelectric aluminum nitride | Nov 2, 2020 | Issued |
Array
(
[id] => 17295410
[patent_doc_number] => 20210391249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => MIMCAP ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 17/081720
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6958
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081720
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081720 | MIMCAP architecture | Oct 26, 2020 | Issued |
Array
(
[id] => 17971417
[patent_doc_number] => 11488966
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => FinFET SRAM having discontinuous PMOS fin lines
[patent_app_type] => utility
[patent_app_number] => 17/080669
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8429
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 274
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080669
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080669 | FinFET SRAM having discontinuous PMOS fin lines | Oct 25, 2020 | Issued |
Array
(
[id] => 17623276
[patent_doc_number] => 11342340
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => Layout of static random access memory periphery circuit
[patent_app_type] => utility
[patent_app_number] => 17/080617
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 11438
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080617
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080617 | Layout of static random access memory periphery circuit | Oct 25, 2020 | Issued |
Array
(
[id] => 20405567
[patent_doc_number] => 12495557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-09
[patent_title] => Method of preparing programmable diode, programmable diode and ferroelectric memory
[patent_app_type] => utility
[patent_app_number] => 18/249890
[patent_app_country] => US
[patent_app_date] => 2020-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18249890
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/249890 | Method of preparing programmable diode, programmable diode and ferroelectric memory | Oct 21, 2020 | Issued |
Array
(
[id] => 17787850
[patent_doc_number] => 11410986
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-09
[patent_title] => Power cell for semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/075968
[patent_app_country] => US
[patent_app_date] => 2020-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 13056
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075968
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/075968 | Power cell for semiconductor devices | Oct 20, 2020 | Issued |
Array
(
[id] => 17574216
[patent_doc_number] => 11322491
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-03
[patent_title] => Integrated grid cell
[patent_app_type] => utility
[patent_app_number] => 17/071909
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10688
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071909
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/071909 | Integrated grid cell | Oct 14, 2020 | Issued |
Array
(
[id] => 17536720
[patent_doc_number] => 20220115329
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => ANTI-TAMPER X-RAY BLOCKING PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/070377
[patent_app_country] => US
[patent_app_date] => 2020-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4706
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070377
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/070377 | Anti-tamper x-ray blocking package | Oct 13, 2020 | Issued |
Array
(
[id] => 17893241
[patent_doc_number] => 11456223
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-27
[patent_title] => Semiconductor stress monitoring structure and semiconductor chip
[patent_app_type] => utility
[patent_app_number] => 17/070237
[patent_app_country] => US
[patent_app_date] => 2020-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5505
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070237
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/070237 | Semiconductor stress monitoring structure and semiconductor chip | Oct 13, 2020 | Issued |
Array
(
[id] => 16699991
[patent_doc_number] => 10950599
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-16
[patent_title] => 3D semiconductor device and structure
[patent_app_type] => utility
[patent_app_number] => 17/064504
[patent_app_country] => US
[patent_app_date] => 2020-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 70
[patent_figures_cnt] => 89
[patent_no_of_words] => 42720
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064504
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/064504 | 3D semiconductor device and structure | Oct 5, 2020 | Issued |