Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17652811 [patent_doc_number] => 11355551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Multi-level magnetic tunnel junction NOR device with wrap-around gate electrodes and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/909080 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 66 [patent_no_of_words] => 12968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909080
Multi-level magnetic tunnel junction NOR device with wrap-around gate electrodes and methods for forming the same Jun 22, 2020 Issued
Array ( [id] => 17803360 [patent_doc_number] => 11417673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Microelectronic devices including stair step structures, and related memory devices, electronic systems, and methods [patent_app_type] => utility [patent_app_number] => 16/908287 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 11063 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908287
Microelectronic devices including stair step structures, and related memory devices, electronic systems, and methods Jun 21, 2020 Issued
Array ( [id] => 16363493 [patent_doc_number] => 20200320244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/908288 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908288
Integrated circuit, system for and method of forming an integrated circuit Jun 21, 2020 Issued
Array ( [id] => 17107519 [patent_doc_number] => 11127745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Devices, methods of forming a device, and memory devices [patent_app_type] => utility [patent_app_number] => 16/906718 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 14433 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906718
Devices, methods of forming a device, and memory devices Jun 18, 2020 Issued
Array ( [id] => 19155101 [patent_doc_number] => 11980037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Memory cells with ferroelectric capacitors separate from transistor gate stacks [patent_app_type] => utility [patent_app_number] => 16/906217 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906217
Memory cells with ferroelectric capacitors separate from transistor gate stacks Jun 18, 2020 Issued
Array ( [id] => 18137329 [patent_doc_number] => 11563018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Microelectronic devices, and related methods, memory devices, and electronic systems [patent_app_type] => utility [patent_app_number] => 16/905385 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14585 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905385
Microelectronic devices, and related methods, memory devices, and electronic systems Jun 17, 2020 Issued
Array ( [id] => 16348456 [patent_doc_number] => 20200313107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/903278 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903278
Light emitting device and fabricating method thereof Jun 15, 2020 Issued
Array ( [id] => 16348156 [patent_doc_number] => 20200312807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/901025 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901025 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901025
Chip package structure Jun 14, 2020 Issued
Array ( [id] => 16528821 [patent_doc_number] => 20200402902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => CONNECTION OF SEVERAL CIRCUITS OF AN ELECTRONIC CHIP [patent_app_type] => utility [patent_app_number] => 16/901449 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901449
Connection of several circuits of an electronic chip Jun 14, 2020 Issued
Array ( [id] => 17652954 [patent_doc_number] => 11355696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Magnetic tunnel junction structures and related methods [patent_app_type] => utility [patent_app_number] => 16/900550 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6306 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900550 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900550
Magnetic tunnel junction structures and related methods Jun 11, 2020 Issued
Array ( [id] => 18372000 [patent_doc_number] => 11652183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Infrared photodetectors [patent_app_type] => utility [patent_app_number] => 16/899759 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4577 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899759
Infrared photodetectors Jun 11, 2020 Issued
Array ( [id] => 17295411 [patent_doc_number] => 20210391250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => VIA STRUCTURES FOR USE IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/899543 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899543
Via structures for use in semiconductor devices Jun 10, 2020 Issued
Array ( [id] => 16545175 [patent_doc_number] => 20200411590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MRAM MEMORY CELL LAYOUT FOR MINIMIZING BITCELL AREA [patent_app_type] => utility [patent_app_number] => 16/893010 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893010
MRAM memory cell layout for minimizing bitcell area Jun 3, 2020 Issued
Array ( [id] => 16316241 [patent_doc_number] => 20200294979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/891139 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891139
Package-on-package (PoP) semiconductor package and electronic system including the same Jun 2, 2020 Issued
Array ( [id] => 17277925 [patent_doc_number] => 20210384123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => WELL-CONTROLLED EDGE-TO-EDGE SPACING BETWEEN ADJACENT INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/891143 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891143 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891143
Well-controlled edge-to-edge spacing between adjacent interconnects Jun 2, 2020 Issued
Array ( [id] => 16858527 [patent_doc_number] => 20210159272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/887541 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887541
Magnetic memory devices May 28, 2020 Issued
Array ( [id] => 16731381 [patent_doc_number] => 20210098529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY DEVICE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/886480 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886480 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886480
Magnetic random access memory device and formation method thereof May 27, 2020 Issued
Array ( [id] => 17263000 [patent_doc_number] => 20210375985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/886648 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886648
Semiconductor structure and method of forming the same May 27, 2020 Issued
Array ( [id] => 17263002 [patent_doc_number] => 20210375987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD FOR MRAM TOP ELECTRODE CONNECTION [patent_app_type] => utility [patent_app_number] => 16/884353 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884353
Method for MRAM top electrode connection May 26, 2020 Issued
Array ( [id] => 16973680 [patent_doc_number] => 11069662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/882517 [patent_app_country] => US [patent_app_date] => 2020-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882517
Semiconductor package and manufacturing method thereof May 23, 2020 Issued
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