Robert A. Rose

Array ( [id] => 16301175 [patent_doc_number] => 20200286898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => Integrated Assemblies Having Dielectric Regions Along Conductive Structures, and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 16/880900 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17438981 [patent_doc_number] => 11264322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/877502 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4946 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17439047 [patent_doc_number] => 11264388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Microelectronic devices including decoupling capacitors, and related apparatuses, electronic systems, and methods [patent_app_type] => utility [patent_app_number] => 16/876362 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11059 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17758127 [patent_doc_number] => 11398426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Integrated-circuit devices and circuitry comprising the same [patent_app_type] => utility [patent_app_number] => 16/876591 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8021 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16973627 [patent_doc_number] => 11069607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Metal option structure of semiconductor device [patent_app_type] => utility [patent_app_number] => 16/876012 [patent_app_country] => US [patent_app_date] => 2020-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6007 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19110263 [patent_doc_number] => 11963397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Display panel, method for manufacturing the same and display device [patent_app_type] => utility [patent_app_number] => 17/280725 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 15392 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17280725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16545038 [patent_doc_number] => 20200411453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => Integrated Circuit Layout, Integrated Circuit, and Method for Fabricating the Same [patent_app_type] => utility [patent_app_number] => 16/869916 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16738924 [patent_doc_number] => 10964588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Selective ILD deposition for fully aligned via with airgap [patent_app_type] => utility [patent_app_number] => 16/868475 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 8412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16516273 [patent_doc_number] => 20200395531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/867138 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17203735 [patent_doc_number] => 20210343830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => METAL-OXIDE-METAL CAPACITOR FROM SUBTRACTIVE BACK-END-OF-LINE SCHEME [patent_app_type] => utility [patent_app_number] => 16/866316 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17075681 [patent_doc_number] => 11112070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Nano-scale light-emitting diode (LED) electrode assembly emitting polarized light, method of manufacturing the same, and polarized led lamp having the same [patent_app_type] => utility [patent_app_number] => 16/866383 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 16126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17590850 [patent_doc_number] => 11329127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Memory device including voids between control gates [patent_app_type] => utility [patent_app_number] => 16/863117 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 17764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19169927 [patent_doc_number] => 11985853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 17/280692 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 19738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 578 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17280692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18176131 [patent_doc_number] => 11575860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Optical control of qubits with spatial light modulators for quantum computing and quantum simulation [patent_app_type] => utility [patent_app_number] => 16/859743 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 10134 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16707844 [patent_doc_number] => 10957788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Semiconductor devices with superjunction structures [patent_app_type] => utility [patent_app_number] => 16/854247 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 9742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17715757 [patent_doc_number] => 11379750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Amplitude, frequency, and phase modulated simultaneous entangling gates for trapped-ion quantum computers [patent_app_type] => utility [patent_app_number] => 16/854043 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16707908 [patent_doc_number] => 10957852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Resistance variable memory structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/853432 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17174466 [patent_doc_number] => 20210328137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => INTERCONNECT STRUCTURES WITH SELECTIVE CAPPING LAYER [patent_app_type] => utility [patent_app_number] => 16/852997 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16707822 [patent_doc_number] => 10957766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Fin-based strap cell structure [patent_app_type] => utility [patent_app_number] => 16/853012 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 18078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17785021 [patent_doc_number] => 11408134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Paving operation control method and system [patent_app_type] => utility [patent_app_number] => 16/852666 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852666 [rel_patent_id] =>[rel_patent_doc_number] =>)