Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15120281 [patent_doc_number] => 20190346773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SEMICONDUCTOR STRUCTURE FOR OPTICAL VALIDATION [patent_app_type] => utility [patent_app_number] => 16/522753 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522753
Semiconductor structure for optical validation Jul 25, 2019 Issued
Array ( [id] => 15093121 [patent_doc_number] => 20190341372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES [patent_app_type] => utility [patent_app_number] => 16/516695 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516695 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516695
Method, apparatus and system to interconnect packaged integrated circuit dies Jul 18, 2019 Issued
Array ( [id] => 15093227 [patent_doc_number] => 20190341425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => THREE DIMENSIONAL MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/513797 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513797 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513797
Three dimensional memory array Jul 16, 2019 Issued
Array ( [id] => 16386513 [patent_doc_number] => 10811358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Hybrid interposer and semiconductor package including the same [patent_app_type] => utility [patent_app_number] => 16/513171 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513171
Hybrid interposer and semiconductor package including the same Jul 15, 2019 Issued
Array ( [id] => 16386483 [patent_doc_number] => 10811328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/513193 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513193
Semiconductor package Jul 15, 2019 Issued
Array ( [id] => 15369731 [patent_doc_number] => 20200020630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => ANTI-FUSE STRUCTURE CIRCUIT AND FORMINFG METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/512869 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512869
Anti-fuse structure circuit and forming method thereof Jul 15, 2019 Issued
Array ( [id] => 16944219 [patent_doc_number] => 11056470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Electronic package and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/513124 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3638 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513124
Electronic package and method for fabricating the same Jul 15, 2019 Issued
Array ( [id] => 19428226 [patent_doc_number] => 12087660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Metal-ceramic substrate with a foil formed for direct cooling as substrate bottom [patent_app_type] => utility [patent_app_number] => 17/259406 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 7193 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17259406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/259406
Metal-ceramic substrate with a foil formed for direct cooling as substrate bottom Jul 10, 2019 Issued
Array ( [id] => 15496531 [patent_doc_number] => 20200048454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => HEAT-CURABLE RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/502791 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502791
Heat-curable resin composition for semiconductor encapsulation and semiconductor device Jul 2, 2019 Issued
Array ( [id] => 15969723 [patent_doc_number] => 20200168613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/502785 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502785 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502785
Semiconductor structure and method for forming the same Jul 2, 2019 Issued
Array ( [id] => 16464215 [patent_doc_number] => 10847578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Three-dimensional resistive memories and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/502833 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502833 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502833
Three-dimensional resistive memories and methods for forming the same Jul 2, 2019 Issued
Array ( [id] => 16410112 [patent_doc_number] => 10818677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Layout of static random access memory periphery circuit [patent_app_type] => utility [patent_app_number] => 16/502790 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502790
Layout of static random access memory periphery circuit Jul 2, 2019 Issued
Array ( [id] => 16339175 [patent_doc_number] => 10790143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => Semiconductor structure, high electron mobility transistor, and method for fabricating semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/502711 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502711
Semiconductor structure, high electron mobility transistor, and method for fabricating semiconductor structure Jul 2, 2019 Issued
Array ( [id] => 15274733 [patent_doc_number] => 20190386101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/455045 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455045
Vertical field effect transistor with reduced gate to source/drain capacitance Jun 26, 2019 Issued
Array ( [id] => 15274735 [patent_doc_number] => 20190386102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/455096 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455096
Vertical field effect transistor with reduced gate to source/drain capacitance Jun 26, 2019 Issued
Array ( [id] => 15274953 [patent_doc_number] => 20190386211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => Sub 60nm Etchless MRAM Devices by Ion Beam Etching Fabricated T-Shaped Bottom Electrode [patent_app_type] => utility [patent_app_number] => 16/452909 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452909 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452909
Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode Jun 25, 2019 Issued
Array ( [id] => 15300133 [patent_doc_number] => 20190393202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => DISPLAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/445777 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445777
Display substrate and fabrication method thereof, display panel and display device Jun 18, 2019 Issued
Array ( [id] => 16594088 [patent_doc_number] => 10903365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Transistors with uniform source/drain epitaxy [patent_app_type] => utility [patent_app_number] => 16/445823 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445823 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445823
Transistors with uniform source/drain epitaxy Jun 18, 2019 Issued
Array ( [id] => 16372597 [patent_doc_number] => 10804363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Three-dimensional semiconductor memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/445815 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 66 [patent_no_of_words] => 12104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445815
Three-dimensional semiconductor memory device and method of fabricating the same Jun 18, 2019 Issued
Array ( [id] => 17310331 [patent_doc_number] => 11211458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Photocatalytic device based on rare-earth elements: methods of manufacture and use [patent_app_type] => utility [patent_app_number] => 16/445789 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4429 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445789
Photocatalytic device based on rare-earth elements: methods of manufacture and use Jun 18, 2019 Issued
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