Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13740855 [patent_doc_number] => 20180374897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => THREE DIMENSIONAL MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/118632 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118632 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118632
Three dimensional memory array Aug 30, 2018 Issued
Array ( [id] => 15733615 [patent_doc_number] => 10615245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/119940 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9979 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119940
Display device Aug 30, 2018 Issued
Array ( [id] => 15547573 [patent_doc_number] => 10573576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Boron nitride nanotube enhanced electrical components [patent_app_type] => utility [patent_app_number] => 16/109391 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 7443 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109391 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109391
Boron nitride nanotube enhanced electrical components Aug 21, 2018 Issued
Array ( [id] => 14738815 [patent_doc_number] => 10388819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Receiver unit [patent_app_type] => utility [patent_app_number] => 15/998506 [patent_app_country] => US [patent_app_date] => 2018-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3319 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15998506 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/998506
Receiver unit Aug 15, 2018 Issued
Array ( [id] => 15250125 [patent_doc_number] => 10510591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-17 [patent_title] => Package-on-package structure and method of manufacturing package [patent_app_type] => utility [patent_app_number] => 16/103937 [patent_app_country] => US [patent_app_date] => 2018-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 6318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103937
Package-on-package structure and method of manufacturing package Aug 14, 2018 Issued
Array ( [id] => 15519635 [patent_doc_number] => 10566416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Semiconductor device with improved field layer [patent_app_type] => utility [patent_app_number] => 16/103949 [patent_app_country] => US [patent_app_date] => 2018-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5265 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103949
Semiconductor device with improved field layer Aug 14, 2018 Issued
Array ( [id] => 15955313 [patent_doc_number] => 10665572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/103939 [patent_app_country] => US [patent_app_date] => 2018-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103939
Semiconductor package and manufacturing method thereof Aug 14, 2018 Issued
Array ( [id] => 13785671 [patent_doc_number] => 20190006374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => FINFET SRAM HAVING DISCONTINUOUS PMOS FIN LINES [patent_app_type] => utility [patent_app_number] => 16/101728 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101728 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101728
FinFET SRAM having discontinuous PMOS fin lines Aug 12, 2018 Issued
Array ( [id] => 15503391 [patent_doc_number] => 20200051884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => STRUCTURES TO FACILITATE HEAT TRANSFER WITHIN PACKAGE LAYERS TO THERMAL HEAT SINK AND MOTHERBOARD [patent_app_type] => utility [patent_app_number] => 16/059513 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059513
Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard Aug 8, 2018 Issued
Array ( [id] => 15519647 [patent_doc_number] => 10566422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Power semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/054472 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054472
Power semiconductor device and method for manufacturing the same Aug 2, 2018 Issued
Array ( [id] => 15462305 [patent_doc_number] => 20200043977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SYMMETRICAL QUBITS WITH REDUCED FAR-FIELD RADIATION [patent_app_type] => utility [patent_app_number] => 16/054326 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054326
Symmetrical qubits with reduced far-field radiation Aug 2, 2018 Issued
Array ( [id] => 15922495 [patent_doc_number] => 10658497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Method for manufacturing semiconductor devices with superjunction structures [patent_app_type] => utility [patent_app_number] => 16/054236 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 9743 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054236
Method for manufacturing semiconductor devices with superjunction structures Aug 2, 2018 Issued
Array ( [id] => 14904409 [patent_doc_number] => 20190295970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/054334 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054334
Semiconductor device Aug 2, 2018 Issued
Array ( [id] => 15139895 [patent_doc_number] => 10483436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Display apparatus and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/053786 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 49 [patent_no_of_words] => 16825 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/053786
Display apparatus and manufacturing method thereof Aug 1, 2018 Issued
Array ( [id] => 16896356 [patent_doc_number] => 11037918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Back-to-back solid state lighting devices and associated methods [patent_app_type] => utility [patent_app_number] => 16/046686 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4079 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046686
Back-to-back solid state lighting devices and associated methods Jul 25, 2018 Issued
Array ( [id] => 14526121 [patent_doc_number] => 10340331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor [patent_app_type] => utility [patent_app_number] => 16/045573 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 11816 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045573
Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor Jul 24, 2018 Issued
Array ( [id] => 15389089 [patent_doc_number] => 10535746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Metal gate structure and methods thereof [patent_app_type] => utility [patent_app_number] => 16/044227 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044227 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/044227
Metal gate structure and methods thereof Jul 23, 2018 Issued
Array ( [id] => 15286745 [patent_doc_number] => 10516043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors [patent_app_type] => utility [patent_app_number] => 16/039370 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 9436 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039370
Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors Jul 18, 2018 Issued
Array ( [id] => 15109271 [patent_doc_number] => 10475968 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Optoelectronic component and a method for producing an optoelectronic component [patent_app_type] => utility [patent_app_number] => 16/039556 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039556
Optoelectronic component and a method for producing an optoelectronic component Jul 18, 2018 Issued
Array ( [id] => 15427979 [patent_doc_number] => 10546929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Optimized double-gate transistors and fabricating process [patent_app_type] => utility [patent_app_number] => 16/039771 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 57 [patent_no_of_words] => 5900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039771 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039771
Optimized double-gate transistors and fabricating process Jul 18, 2018 Issued
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