Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18991329 [patent_doc_number] => 20240063298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/234210 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234210
SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF Aug 14, 2023 Pending
Array ( [id] => 19773437 [patent_doc_number] => 20250054863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => FLEXIBLE TRACKPLAN FOR POWER DELIVERY [patent_app_type] => utility [patent_app_number] => 18/448933 [patent_app_country] => US [patent_app_date] => 2023-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448933
FLEXIBLE TRACKPLAN FOR POWER DELIVERY Aug 11, 2023 Pending
Array ( [id] => 18975256 [patent_doc_number] => 20240055348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => THREE DIMENSIONAL INTEGRATED CIRCUIT WITH MONOLITHIC INTER-TIER VIAS (MIV) [patent_app_type] => utility [patent_app_number] => 18/447739 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447739
Three dimensional integrated circuit with monolithic inter-tier vias (MIV) Aug 9, 2023 Issued
Array ( [id] => 19906535 [patent_doc_number] => 12283554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Integrated circuit layout, integrated circuit, and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/447840 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 58 [patent_no_of_words] => 38323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447840
Integrated circuit layout, integrated circuit, and method for fabricating the same Aug 9, 2023 Issued
Array ( [id] => 19925089 [patent_doc_number] => 12299373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Reduced area standard cell abutment configurations [patent_app_type] => utility [patent_app_number] => 18/447187 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 6549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447187
Reduced area standard cell abutment configurations Aug 8, 2023 Issued
Array ( [id] => 19873777 [patent_doc_number] => 12266648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Package structure [patent_app_type] => utility [patent_app_number] => 18/363768 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 11638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363768
Package structure Aug 1, 2023 Issued
Array ( [id] => 19758087 [patent_doc_number] => 20250046652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => FABRICATING DUAL DAMASCENE STRUCTURES USING MULTILAYER PHOTOSENSITIVE DIELECTRICS [patent_app_type] => utility [patent_app_number] => 18/228846 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228846
Fabricating dual damascene structures using multilayer photosensitive dielectrics Jul 31, 2023 Issued
Array ( [id] => 18791191 [patent_doc_number] => 20230380187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MRAM MEMORY CELL LAYOUT FOR MINIMIZING BITCELL AREA [patent_app_type] => utility [patent_app_number] => 18/362817 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362817
MRAM memory cell layout for minimizing bitcell area Jul 30, 2023 Issued
Array ( [id] => 19101048 [patent_doc_number] => 20240120276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING INTER-DIE INTERFACE [patent_app_type] => utility [patent_app_number] => 18/227113 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227113
Three-dimensional semiconductor integrated circuit device including inter-die interface Jul 26, 2023 Issued
Array ( [id] => 18776557 [patent_doc_number] => 20230371399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => UNDER-CUT VIA ELECTRODE FOR SUB 60NM ETCHLESS MRAM DEVICES BY DECOUPLING THE VIA ETCH PROCESS [patent_app_type] => utility [patent_app_number] => 18/360055 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360055
Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process Jul 26, 2023 Issued
Array ( [id] => 18757642 [patent_doc_number] => 20230361105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/355273 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355273
Integrated circuit device and method Jul 18, 2023 Issued
Array ( [id] => 20404448 [patent_doc_number] => 12494429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Power planning method, chip device, and non-transitory computer readable medium [patent_app_type] => utility [patent_app_number] => 18/223069 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223069
Power planning method, chip device, and non-transitory computer readable medium Jul 17, 2023 Issued
Array ( [id] => 19886946 [patent_doc_number] => 12272678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/351471 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351471
Semiconductor package and manufacturing method thereof Jul 11, 2023 Issued
Array ( [id] => 19712653 [patent_doc_number] => 20250022795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => BACKSIDE LOCAL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/349999 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349999 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349999
BACKSIDE LOCAL INTERCONNECT Jul 10, 2023 Pending
Array ( [id] => 20404421 [patent_doc_number] => 12494402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/349685 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349685
Semiconductor device Jul 9, 2023 Issued
Array ( [id] => 18745694 [patent_doc_number] => 20230354688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHOD FOR SELECTIVELY DEPOSITING A CONDUCTIVE COATING OVER A PATTERNING COATING AND DEVICE INCLUDING A CONDUCTIVE COATING [patent_app_type] => utility [patent_app_number] => 18/348282 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -46 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348282
Method for selectively depositing a conductive coating over a patterning coating and device including a conductive coating Jul 5, 2023 Issued
Array ( [id] => 18743410 [patent_doc_number] => 20230352398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Metal-Oxide-Metal (MOM) Capacitors for Integrated Circuit Monitoring [patent_app_type] => utility [patent_app_number] => 18/218197 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218197 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218197
Metal-oxide-metal (MOM) capacitors for integrated circuit monitoring Jul 4, 2023 Issued
Array ( [id] => 20082536 [patent_doc_number] => 12356633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor devices and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/347536 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347536
Semiconductor devices and method of forming the same Jul 4, 2023 Issued
Array ( [id] => 18745615 [patent_doc_number] => 20230354609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS [patent_app_type] => utility [patent_app_number] => 18/346504 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 64858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346504
METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS Jul 2, 2023 Pending
Array ( [id] => 18745597 [patent_doc_number] => 20230354591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INTEGRATED CIRCUIT LAYOUT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/346700 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346700
Integrated circuit layout and method Jul 2, 2023 Issued
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