Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12897271 [patent_doc_number] => 20180190932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => Organic Light Emitting Device [patent_app_type] => utility [patent_app_number] => 15/593029 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593029
Organic light emitting device May 10, 2017 Issued
Array ( [id] => 12631131 [patent_doc_number] => 20180102207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => PATTERNING MAGNETIC FILMS USING SELF-STOP ELECTRO-ETCHING [patent_app_type] => utility [patent_app_number] => 15/587685 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587685 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587685
Patterning magnetic films using self-stop electro-etching May 4, 2017 Issued
Array ( [id] => 11869469 [patent_doc_number] => 20170236754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'Integrated Clip and Lead and Method of Making a Circuit' [patent_app_type] => utility [patent_app_number] => 15/585519 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3060 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585519
Integrated clip and lead and method of making a circuit May 2, 2017 Issued
Array ( [id] => 12062006 [patent_doc_number] => 20170338349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/585849 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 31683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585849 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585849
SEMICONDUCTOR DEVICE AND MEMORY DEVICE May 2, 2017 Abandoned
Array ( [id] => 13543195 [patent_doc_number] => 20180323144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => MULTI-DIE INDUCTORS WITH COUPLED THROUGH-SUBSTRATE VIA CORES [patent_app_type] => utility [patent_app_number] => 15/584881 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584881
Multi-die inductors with coupled through-substrate via cores May 1, 2017 Issued
Array ( [id] => 12554724 [patent_doc_number] => 10014468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Barrier layer for correlated electron material [patent_app_type] => utility [patent_app_number] => 15/499212 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12199 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499212
Barrier layer for correlated electron material Apr 26, 2017 Issued
Array ( [id] => 14177947 [patent_doc_number] => 10262994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => FinFET LDMOS devices with additional dynamic control [patent_app_type] => utility [patent_app_number] => 15/495236 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5064 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495236
FinFET LDMOS devices with additional dynamic control Apr 23, 2017 Issued
Array ( [id] => 12457200 [patent_doc_number] => 09984937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-29 [patent_title] => Vertical silicon/silicon-germanium transistors with multiple threshold voltages [patent_app_type] => utility [patent_app_number] => 15/492615 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5970 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492615 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492615
Vertical silicon/silicon-germanium transistors with multiple threshold voltages Apr 19, 2017 Issued
Array ( [id] => 13071209 [patent_doc_number] => 10056390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => FinFET SRAM having discontinuous PMOS fin lines [patent_app_type] => utility [patent_app_number] => 15/492777 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492777 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492777
FinFET SRAM having discontinuous PMOS fin lines Apr 19, 2017 Issued
Array ( [id] => 12256979 [patent_doc_number] => 09929128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Chip package structure with adhesive layer' [patent_app_type] => utility [patent_app_number] => 15/492617 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492617 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492617
Chip package structure with adhesive layer Apr 19, 2017 Issued
Array ( [id] => 13071157 [patent_doc_number] => 10056364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Electronic device with adjustable reverse breakdown voltage [patent_app_type] => utility [patent_app_number] => 15/481882 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481882
Electronic device with adjustable reverse breakdown voltage Apr 6, 2017 Issued
Array ( [id] => 13485539 [patent_doc_number] => 20180294312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => THREE DIMENSIONAL MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/482016 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482016
Three dimensional memory array Apr 6, 2017 Issued
Array ( [id] => 12498552 [patent_doc_number] => 09997478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-12 [patent_title] => Circuits and antennas integrated in dies and corresponding method [patent_app_type] => utility [patent_app_number] => 15/481910 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6867 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481910
Circuits and antennas integrated in dies and corresponding method Apr 6, 2017 Issued
Array ( [id] => 12436545 [patent_doc_number] => 09978699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-22 [patent_title] => Three-dimensional complementary-conducting-strip structure [patent_app_type] => utility [patent_app_number] => 15/481872 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 52 [patent_no_of_words] => 5756 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481872 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481872
Three-dimensional complementary-conducting-strip structure Apr 6, 2017 Issued
Array ( [id] => 12215003 [patent_doc_number] => 09911819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Circuits using gate-all-around technology' [patent_app_type] => utility [patent_app_number] => 15/479803 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 12557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479803
Circuits using gate-all-around technology Apr 4, 2017 Issued
Array ( [id] => 12554202 [patent_doc_number] => 10014292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => 3D semiconductor device and structure [patent_app_type] => utility [patent_app_number] => 15/477106 [patent_app_country] => US [patent_app_date] => 2017-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 115 [patent_figures_cnt] => 141 [patent_no_of_words] => 64999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477106
3D semiconductor device and structure Apr 1, 2017 Issued
Array ( [id] => 13159605 [patent_doc_number] => 10096537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Thermal management systems, methods for making, and methods for using [patent_app_type] => utility [patent_app_number] => 15/475074 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 79 [patent_no_of_words] => 35589 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475074
Thermal management systems, methods for making, and methods for using Mar 29, 2017 Issued
Array ( [id] => 12416778 [patent_doc_number] => 09972539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/475097 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3140 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475097
Method of fabricating semiconductor device Mar 29, 2017 Issued
Array ( [id] => 14177943 [patent_doc_number] => 10262992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Three dimensional LVDMOS transistor structures [patent_app_type] => utility [patent_app_number] => 15/472585 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6472 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472585
Three dimensional LVDMOS transistor structures Mar 28, 2017 Issued
Array ( [id] => 13995993 [patent_doc_number] => 20190067154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => POWER MODULE, POWER SEMICONDUCTOR DEVICE AND POWER MODULE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/070839 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070839
Power module, power semiconductor device and power module manufacturing method Mar 26, 2017 Issued
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