Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12355341 [patent_doc_number] => 09953959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Metal protected fan-out cavity [patent_app_type] => utility [patent_app_number] => 15/463523 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 11006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463523
Metal protected fan-out cavity Mar 19, 2017 Issued
Array ( [id] => 12263835 [patent_doc_number] => 20180083031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/463582 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463582
Semiconductor memory device and method for manufacturing same Mar 19, 2017 Issued
Array ( [id] => 13031031 [patent_doc_number] => 10038141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Fabrication of correlated electron material devices [patent_app_type] => utility [patent_app_number] => 15/463546 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 10193 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463546
Fabrication of correlated electron material devices Mar 19, 2017 Issued
Array ( [id] => 12257086 [patent_doc_number] => 09929235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 15/463551 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 12525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463551
Semiconductor device and method for fabricating the same Mar 19, 2017 Issued
Array ( [id] => 13640777 [patent_doc_number] => 09847349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-19 [patent_title] => Biasing the substrate region of an MOS transistor [patent_app_type] => utility [patent_app_number] => 15/463493 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2435 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463493
Biasing the substrate region of an MOS transistor Mar 19, 2017 Issued
Array ( [id] => 12396270 [patent_doc_number] => 09966345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-08 [patent_title] => Protective barrier for integrated circuit packages housing a voltage regulator and a load [patent_app_type] => utility [patent_app_number] => 15/463627 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463627
Protective barrier for integrated circuit packages housing a voltage regulator and a load Mar 19, 2017 Issued
Array ( [id] => 12436989 [patent_doc_number] => 09978847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit [patent_app_type] => utility [patent_app_number] => 15/454184 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2320 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454184
Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit Mar 8, 2017 Issued
Array ( [id] => 12154681 [patent_doc_number] => 20180025945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'PNP-TYPE BIPOLAR TRANSISTOR MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/450114 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3609 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450114
PNP-type bipolar transistor manufacturing method Mar 5, 2017 Issued
Array ( [id] => 12115067 [patent_doc_number] => 09871063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-16 [patent_title] => 'Display driver semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/450083 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450083
Display driver semiconductor device and manufacturing method thereof Mar 5, 2017 Issued
Array ( [id] => 14346293 [patent_doc_number] => 20190155119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/084260 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16084260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/084260
Semiconductor apparatus and method for manufacturing semiconductor apparatus Mar 2, 2017 Issued
Array ( [id] => 11694356 [patent_doc_number] => 20170170073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch' [patent_app_type] => utility [patent_app_number] => 15/443527 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443527
Method and structure to fabricate closely packed hybrid nanowires at scaled pitch Feb 26, 2017 Issued
Array ( [id] => 11666322 [patent_doc_number] => 20170155041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'ARMATURE-CLAD MRAM DEVICE' [patent_app_type] => utility [patent_app_number] => 15/432409 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432409
Armature-clad MRAM device Feb 13, 2017 Issued
Array ( [id] => 11694349 [patent_doc_number] => 20170170066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'Method of Semiconductor Integrated Circuit Fabrication' [patent_app_type] => utility [patent_app_number] => 15/430852 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430852 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430852
Method of semiconductor integrated circuit fabrication Feb 12, 2017 Issued
Array ( [id] => 12256935 [patent_doc_number] => 09929084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Device with interconnection structure for forming a conduction path or a conducting plane with high decoupling capacitance' [patent_app_type] => utility [patent_app_number] => 15/428502 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 11094 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428502 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428502
Device with interconnection structure for forming a conduction path or a conducting plane with high decoupling capacitance Feb 8, 2017 Issued
Array ( [id] => 12990337 [patent_doc_number] => 20170345855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => LOW NOISE DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/428356 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428356
Low noise device and method of forming the same Feb 8, 2017 Issued
Array ( [id] => 11967171 [patent_doc_number] => 20170271324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/428498 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 19922 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428498
Semiconductor device and method of manufacturing semiconductor device Feb 8, 2017 Issued
Array ( [id] => 13043179 [patent_doc_number] => 10043729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-07 [patent_title] => Power electronics module [patent_app_type] => utility [patent_app_number] => 15/428471 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2704 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428471
Power electronics module Feb 8, 2017 Issued
Array ( [id] => 15234039 [patent_doc_number] => 10504749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/070893 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7658 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070893
Semiconductor device Feb 6, 2017 Issued
Array ( [id] => 11904529 [patent_doc_number] => 09773972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Magnetic device' [patent_app_type] => utility [patent_app_number] => 15/420091 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420091
Magnetic device Jan 29, 2017 Issued
Array ( [id] => 13328143 [patent_doc_number] => 20180215609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => INTEGRATED PARTICLE FILTER FOR MEMS DEVICE [patent_app_type] => utility [patent_app_number] => 15/419663 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419663
Integrated particle filter for MEMS device Jan 29, 2017 Issued
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