Robert A. Rose

Array ( [id] => 11032732 [patent_doc_number] => 20160229688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'STRESS RELIEF MEMS STRUCTURE AND PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/616017 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4720 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11585957 [patent_doc_number] => 09640610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/109597 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 11681 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15109597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10638522 [patent_doc_number] => 09356034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Multilevel interconnect structure and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/614757 [patent_app_country] => US [patent_app_date] => 2015-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 20157 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10638505 [patent_doc_number] => 09356017 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Switch circuit and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/614578 [patent_app_country] => US [patent_app_date] => 2015-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11028661 [patent_doc_number] => 20160225618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'REDUCING SUBSTRATE BOWING CAUSED BY HIGH PERCENTAGE SIGE LAYERS' [patent_app_type] => utility [patent_app_number] => 14/613419 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14613419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10590734 [patent_doc_number] => 09312356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-12 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/613379 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4595 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14613379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11776188 [patent_doc_number] => 09385140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-05 [patent_title] => 'Efficient buried oxide layer interconnect scheme' [patent_app_type] => utility [patent_app_number] => 14/614395 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11207926 [patent_doc_number] => 09437558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'High frequency integrated circuit and packaging for same' [patent_app_type] => utility [patent_app_number] => 14/613005 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6200 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14613005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10687688 [patent_doc_number] => 20160033833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'PIXEL ARRAY' [patent_app_type] => utility [patent_app_number] => 14/612298 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7355 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11233693 [patent_doc_number] => 09460928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Method for manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/612359 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 4275 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11770484 [patent_doc_number] => 09379182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-28 [patent_title] => 'Method for forming nanowire and semiconductor device formed with the nanowire' [patent_app_type] => utility [patent_app_number] => 14/612352 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 56 [patent_no_of_words] => 3727 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11028852 [patent_doc_number] => 20160225809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'OVERMOLDED RECONSTRUCTED CAMERA MODULE' [patent_app_type] => utility [patent_app_number] => 14/611950 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597342 [patent_doc_number] => 09318437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-19 [patent_title] => 'Moisture scavenging layer for thinner barrier application in beol integration' [patent_app_type] => utility [patent_app_number] => 14/611740 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11007151 [patent_doc_number] => 20160204103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'SEMICONDUCTOR DEVICE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/611843 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4448 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10611032 [patent_doc_number] => 09331074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-03 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/611159 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10758522 [patent_doc_number] => 20160104674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'INTEGRATED CIRCUIT WITH ELONGATED COUPLING' [patent_app_type] => utility [patent_app_number] => 14/610294 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597383 [patent_doc_number] => 09318478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-19 [patent_title] => 'Semiconductor device and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 14/610046 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11174171 [patent_doc_number] => 09406772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-02 [patent_title] => 'Semiconductor structure with a multilayer gate oxide and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/609446 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2615 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11028812 [patent_doc_number] => 20160225768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'III-V CMOS INTEGRATION ON SILICON SUBSTRATE VIA EMBEDDED GERMANIUM-CONTAINING LAYER' [patent_app_type] => utility [patent_app_number] => 14/609507 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10584035 [patent_doc_number] => 09306164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-05 [patent_title] => 'Electrode pair fabrication using directed self assembly of diblock copolymers' [patent_app_type] => utility [patent_app_number] => 14/609709 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4463 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609709 [rel_patent_id] =>[rel_patent_doc_number] =>)