Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11043572 [patent_doc_number] => 20160240528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'IGBT WITH BUILT-IN DIODE AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/901622 [patent_app_country] => US [patent_app_date] => 2014-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5191 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/901622
IGBT with built-in diode and manufacturing method therefor Jun 8, 2014 Issued
Array ( [id] => 11043652 [patent_doc_number] => 20160240608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'FIELD-STOP REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/901606 [patent_app_country] => US [patent_app_date] => 2014-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3983 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/901606
Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor Jun 5, 2014 Issued
Array ( [id] => 10993453 [patent_doc_number] => 20160190400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'LIGHT-EMITTING DEVICE PACKAGE, MANUFACTURING METHOD THEREOF, AND VEHICLE LAMP AND BACKLIGHT UNIT INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 14/891304 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11674 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14891304 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/891304
Light-emitting device package, manufacturing method thereof, and vehicle lamp and backlight unit including same May 12, 2014 Issued
Array ( [id] => 10111682 [patent_doc_number] => 09147100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Method for enhancing surface characteristics of a fingerprint sensor and structure made of the same' [patent_app_type] => utility [patent_app_number] => 14/273743 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2472 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273743 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273743
Method for enhancing surface characteristics of a fingerprint sensor and structure made of the same May 8, 2014 Issued
Array ( [id] => 11207945 [patent_doc_number] => 09437577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Package on package structure with pillar bump pins and related method thereof' [patent_app_type] => utility [patent_app_number] => 14/273553 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1532 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273553 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273553
Package on package structure with pillar bump pins and related method thereof May 8, 2014 Issued
Array ( [id] => 10439120 [patent_doc_number] => 20150324131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SYSTEM AND METHOD FOR MEMORY ALLOCATION IN A MULTICLASS MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/273751 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273751 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273751
System and method for memory allocation in a multiclass memory system May 8, 2014 Issued
Array ( [id] => 10112253 [patent_doc_number] => 09147672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Three-dimensional multiple chip packages including multiple chip stacks' [patent_app_type] => utility [patent_app_number] => 14/273171 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273171 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273171
Three-dimensional multiple chip packages including multiple chip stacks May 7, 2014 Issued
Array ( [id] => 10343562 [patent_doc_number] => 20150228567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/273306 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3183 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273306 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273306
PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE USING THE SAME May 7, 2014 Abandoned
Array ( [id] => 10402788 [patent_doc_number] => 20150287797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'HIGH-VOLTAGE METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/273538 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4027 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273538 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273538
High-voltage metal-oxide semiconductor transistor and method of fabricating the same May 7, 2014 Issued
Array ( [id] => 10112404 [patent_doc_number] => 09147824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Reactive contacts for 2D layered metal dichalcogenides' [patent_app_type] => utility [patent_app_number] => 14/272889 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272889
Reactive contacts for 2D layered metal dichalcogenides May 7, 2014 Issued
Array ( [id] => 10519075 [patent_doc_number] => 09246132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Flexible organic light-emitting display apparatus and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/273466 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2823 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273466
Flexible organic light-emitting display apparatus and method of manufacturing the same May 7, 2014 Issued
Array ( [id] => 10145046 [patent_doc_number] => 09177858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-03 [patent_title] => 'Methods for fabricating integrated circuits including barrier layers for interconnect structures' [patent_app_type] => utility [patent_app_number] => 14/272787 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272787
Methods for fabricating integrated circuits including barrier layers for interconnect structures May 7, 2014 Issued
Array ( [id] => 10577095 [patent_doc_number] => 09299745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/272916 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272916 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272916
Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same May 7, 2014 Issued
Array ( [id] => 10440575 [patent_doc_number] => 20150325587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => '3D STACKED IC DEVICE WITH STEPPED SUBSTACK INTERLAYER CONNECTORS' [patent_app_type] => utility [patent_app_number] => 14/273206 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8306 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273206 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273206
3D stacked IC device with stepped substack interlayer connectors May 7, 2014 Issued
Array ( [id] => 10035323 [patent_doc_number] => 09076645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-07 [patent_title] => 'Method of fabricating an interlayer structure of increased elasticity modulus' [patent_app_type] => utility [patent_app_number] => 14/272554 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272554 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272554
Method of fabricating an interlayer structure of increased elasticity modulus May 7, 2014 Issued
Array ( [id] => 10563785 [patent_doc_number] => 09287467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Techniques for adhering surface mount devices to a flexible substrate' [patent_app_type] => utility [patent_app_number] => 14/273054 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 5209 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273054
Techniques for adhering surface mount devices to a flexible substrate May 7, 2014 Issued
Array ( [id] => 10537660 [patent_doc_number] => 09263294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Method of forming semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/273283 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4085 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273283
Method of forming semiconductor device May 7, 2014 Issued
Array ( [id] => 10440623 [patent_doc_number] => 20150325635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/271515 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271515 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271515
Metal-insulator-metal back end of line capacitor structures May 6, 2014 Issued
Array ( [id] => 10093223 [patent_doc_number] => 09130055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Magnetic recording head with CPP-GMR spin-valve sensor and extended pinned layer' [patent_app_type] => utility [patent_app_number] => 14/272381 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 11440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272381 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272381
Magnetic recording head with CPP-GMR spin-valve sensor and extended pinned layer May 6, 2014 Issued
Array ( [id] => 10440885 [patent_doc_number] => 20150325897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'ELECTRICALLY CONTROLLABLE RADIO-FREQUENCY CIRCUIT ELEMENT HAVING AN ELECTROCHROMIC MATERIAL' [patent_app_type] => utility [patent_app_number] => 14/271970 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6043 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271970
ELECTRICALLY CONTROLLABLE RADIO-FREQUENCY CIRCUIT ELEMENT HAVING AN ELECTROCHROMIC MATERIAL May 6, 2014 Abandoned
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