Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10093132 [patent_doc_number] => 09129962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Bonding pad arrangment design for multi-die semiconductor package structure' [patent_app_type] => utility [patent_app_number] => 14/271792 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5985 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271792 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271792
Bonding pad arrangment design for multi-die semiconductor package structure May 6, 2014 Issued
Array ( [id] => 10092992 [patent_doc_number] => 09129821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Electrostatic discharge protection device' [patent_app_type] => utility [patent_app_number] => 14/272162 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3258 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272162 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272162
Electrostatic discharge protection device May 6, 2014 Issued
Array ( [id] => 10530431 [patent_doc_number] => 09256567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Storage device with expansion slot' [patent_app_type] => utility [patent_app_number] => 14/271905 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271905 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271905
Storage device with expansion slot May 6, 2014 Issued
Array ( [id] => 10440554 [patent_doc_number] => 20150325565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'Composite Semiconductor Device with Multiple Threshold Voltages' [patent_app_type] => utility [patent_app_number] => 14/272027 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272027 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272027
Composite semiconductor device with multiple threshold voltages May 6, 2014 Issued
Array ( [id] => 10022225 [patent_doc_number] => 09064718 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Pre-formed via array for integrated circuit package' [patent_app_type] => utility [patent_app_number] => 14/271469 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5220 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271469 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271469
Pre-formed via array for integrated circuit package May 6, 2014 Issued
Array ( [id] => 10073484 [patent_doc_number] => 09111848 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-18 [patent_title] => 'Cascaded test chain for stuck-at fault verification' [patent_app_type] => utility [patent_app_number] => 14/272324 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 15292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272324 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272324
Cascaded test chain for stuck-at fault verification May 6, 2014 Issued
Array ( [id] => 10440484 [patent_doc_number] => 20150325496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'INTEGRATED DEVICE COMPRISING WIRES AS VIAS IN AN ENCAPSULATION LAYER' [patent_app_type] => utility [patent_app_number] => 14/272494 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8995 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272494 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272494
Integrated device comprising wires as vias in an encapsulation layer May 6, 2014 Issued
Array ( [id] => 10440657 [patent_doc_number] => 20150325668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/272133 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6822 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272133
Semiconductor device and method for fabricating the same May 6, 2014 Issued
Array ( [id] => 10041918 [patent_doc_number] => 09082631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-14 [patent_title] => 'Linear equalizer circuit and method thereof' [patent_app_type] => utility [patent_app_number] => 14/271509 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2767 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271509
Linear equalizer circuit and method thereof May 6, 2014 Issued
Array ( [id] => 9682619 [patent_doc_number] => 20140239382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD' [patent_app_type] => utility [patent_app_number] => 14/270228 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7699 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270228 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270228
High frequency switching MOSFETs with low output capacitance using a depletable P-shield May 4, 2014 Issued
Array ( [id] => 10151910 [patent_doc_number] => 09184206 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-10 [patent_title] => 'Backside illuminated color image sensors and methods for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/270309 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270309
Backside illuminated color image sensors and methods for manufacturing the same May 4, 2014 Issued
Array ( [id] => 10531411 [patent_doc_number] => 09257556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Silicon germanium FinFET formation by Ge condensation' [patent_app_type] => utility [patent_app_number] => 14/269981 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5334 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269981 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/269981
Silicon germanium FinFET formation by Ge condensation May 4, 2014 Issued
Array ( [id] => 10238091 [patent_doc_number] => 20150123085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/270285 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270285 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270285
Display apparatus and method of manufacturing the same May 4, 2014 Issued
Array ( [id] => 11211403 [patent_doc_number] => 09440424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Methods to form and to dismantle hermetically sealed chambers' [patent_app_type] => utility [patent_app_number] => 14/270265 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4686 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270265
Methods to form and to dismantle hermetically sealed chambers May 4, 2014 Issued
Array ( [id] => 10060300 [patent_doc_number] => 09099663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-04 [patent_title] => 'Quantum dot solar cells with band alignment engineering' [patent_app_type] => utility [patent_app_number] => 14/268772 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 6277 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268772
Quantum dot solar cells with band alignment engineering May 1, 2014 Issued
Array ( [id] => 10165979 [patent_doc_number] => 09197215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-24 [patent_title] => 'Graphene-based non-boolean logic circuits' [patent_app_type] => utility [patent_app_number] => 14/268765 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 8704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268765 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268765
Graphene-based non-boolean logic circuits May 1, 2014 Issued
Array ( [id] => 10321850 [patent_doc_number] => 20150206854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A REDISTRIBUTION LAYER' [patent_app_type] => utility [patent_app_number] => 14/268974 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268974
Package on package (PoP) integrated device comprising a redistribution layer May 1, 2014 Issued
Array ( [id] => 10022437 [patent_doc_number] => 09064932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Methods of forming gate structures by a gate-cut-last process and the resulting structures' [patent_app_type] => utility [patent_app_number] => 14/268478 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 5946 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268478
Methods of forming gate structures by a gate-cut-last process and the resulting structures May 1, 2014 Issued
Array ( [id] => 10433334 [patent_doc_number] => 20150318347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'Semiconductor Device with a Field Ring Edge Termination Structure and a Separation Trench Arranged Between Different Field Rings' [patent_app_type] => utility [patent_app_number] => 14/268033 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5775 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268033 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268033
Semiconductor device with a field ring edge termination structure and a separation trench arranged between different field rings May 1, 2014 Issued
Array ( [id] => 10028646 [patent_doc_number] => 09070552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-30 [patent_title] => 'Adaptive standard cell architecture and layout techniques for low area digital SoC' [patent_app_type] => utility [patent_app_number] => 14/267888 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4116 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267888 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267888
Adaptive standard cell architecture and layout techniques for low area digital SoC Apr 30, 2014 Issued
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