Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8884271 [patent_doc_number] => 20130157455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'Electrical Contact Alignment Posts' [patent_app_type] => utility [patent_app_number] => 13/765280 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765280
Electrical contact alignment posts Feb 11, 2013 Issued
Array ( [id] => 8838875 [patent_doc_number] => 20130134503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS' [patent_app_type] => utility [patent_app_number] => 13/751902 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5214 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/751902
Cross-point diode arrays and methods of manufacturing cross-point diode arrays Jan 27, 2013 Issued
Array ( [id] => 9427466 [patent_doc_number] => 08703540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Chip-scale semiconductor die packaging method' [patent_app_type] => utility [patent_app_number] => 13/742252 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9008 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/742252
Chip-scale semiconductor die packaging method Jan 14, 2013 Issued
Array ( [id] => 9557887 [patent_doc_number] => 20140175599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE WITH PRINTED CIRCUIT LAYER' [patent_app_type] => utility [patent_app_number] => 13/723874 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723874
Integrated circuit package with printed circuit layer Dec 20, 2012 Issued
Array ( [id] => 9345611 [patent_doc_number] => 08664761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'Semiconductor structure and manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 13/723255 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 52 [patent_no_of_words] => 5940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723255 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723255
Semiconductor structure and manufacturing method of the same Dec 20, 2012 Issued
Array ( [id] => 9557802 [patent_doc_number] => 20140175514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'RING-SHAPED TRANSISTORS PROVIDING REDUCED SELF-HEATING' [patent_app_type] => utility [patent_app_number] => 13/724598 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724598 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724598
Ring-shaped transistors providing reduced self-heating Dec 20, 2012 Issued
Array ( [id] => 9557847 [patent_doc_number] => 20140175560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/723272 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3619 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723272 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723272
Semiconductor structure and method for manufacturing the same Dec 20, 2012 Issued
Array ( [id] => 9691715 [patent_doc_number] => 08822309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Heterogeneous integration process incorporating layer transfer in epitaxy level packaging' [patent_app_type] => utility [patent_app_number] => 13/724701 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4751 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724701 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724701
Heterogeneous integration process incorporating layer transfer in epitaxy level packaging Dec 20, 2012 Issued
Array ( [id] => 9316592 [patent_doc_number] => 20140048930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'CONDUCTIVE BUMP, SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/723992 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5513 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723992
Conductive bump, semiconductor chip and stacked semiconductor package using the same Dec 20, 2012 Issued
Array ( [id] => 9627113 [patent_doc_number] => 08796797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same' [patent_app_type] => utility [patent_app_number] => 13/723893 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7704 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723893 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723893
Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same Dec 20, 2012 Issued
Array ( [id] => 8888491 [patent_doc_number] => 20130161675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/724398 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724398 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724398
Light emitting device Dec 20, 2012 Issued
Array ( [id] => 9557659 [patent_doc_number] => 20140175371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'VERTICAL CROSS-POINT EMBEDDED MEMORY ARCHITECTURE FOR METAL-CONDUCTIVE OXIDE-METAL (MCOM) MEMORY ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/723876 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7777 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723876 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723876
VERTICAL CROSS-POINT EMBEDDED MEMORY ARCHITECTURE FOR METAL-CONDUCTIVE OXIDE-METAL (MCOM) MEMORY ELEMENTS Dec 20, 2012 Abandoned
Array ( [id] => 9557951 [patent_doc_number] => 20140175664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'DIELECTRIC SOLDER BARRIER FOR SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/724426 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3665 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724426
Dielectric solder barrier for semiconductor devices Dec 20, 2012 Issued
Array ( [id] => 9530084 [patent_doc_number] => 08753956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Semiconductor structure and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/724284 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724284 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724284
Semiconductor structure and fabrication method Dec 20, 2012 Issued
Array ( [id] => 9649121 [patent_doc_number] => 08803137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Organic light emitting display device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/723797 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 11199 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723797 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723797
Organic light emitting display device and method for manufacturing the same Dec 20, 2012 Issued
Array ( [id] => 9557951 [patent_doc_number] => 20140175664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'DIELECTRIC SOLDER BARRIER FOR SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/724426 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3665 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724426
Dielectric solder barrier for semiconductor devices Dec 20, 2012 Issued
Array ( [id] => 9711483 [patent_doc_number] => 08836059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Shape enhanced pin read head magnetic transducer with stripe height defined first and method of making same' [patent_app_type] => utility [patent_app_number] => 13/724662 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 7108 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724662
Shape enhanced pin read head magnetic transducer with stripe height defined first and method of making same Dec 20, 2012 Issued
Array ( [id] => 9557870 [patent_doc_number] => 20140175583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME' [patent_app_type] => utility [patent_app_number] => 13/723866 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8834 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723866 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723866
Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same Dec 20, 2012 Issued
Array ( [id] => 9345573 [patent_doc_number] => 08664723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'Integrated circuit structures having base resistance tuning regions and methods for forming the same' [patent_app_type] => utility [patent_app_number] => 13/723993 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723993 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723993
Integrated circuit structures having base resistance tuning regions and methods for forming the same Dec 20, 2012 Issued
Array ( [id] => 9557951 [patent_doc_number] => 20140175664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'DIELECTRIC SOLDER BARRIER FOR SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/724426 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3665 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724426
Dielectric solder barrier for semiconductor devices Dec 20, 2012 Issued
Menu