Search

Robert A. Rose

Examiner (ID: 12998, Phone: (571)272-4494 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3723, 3727, 3203, 2899
Total Applications
3154
Issued Applications
2531
Pending Applications
105
Abandoned Applications
520

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20484032 [patent_doc_number] => 12532511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Barrier layers in semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/116209 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 3042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/116209
Barrier layers in semiconductor devices Feb 28, 2023 Issued
Array ( [id] => 19101045 [patent_doc_number] => 20240120273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => DEVICE WITH GATE-TO-DRAIN VIA AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/172246 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172246
Device with gate-to-drain via and related methods Feb 20, 2023 Issued
Array ( [id] => 18440125 [patent_doc_number] => 20230187420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => WHITE LIGHT EMITTING DEVICES HAVING HIGH LUMINOUS EFFICIENCY AND IMPROVED COLOR RENDERING THAT INCLUDE PASS-THROUGH VIOLET EMISSIONS [patent_app_type] => utility [patent_app_number] => 18/109554 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109554
White light emitting devices having high luminous efficiency and improved color rendering that include pass-through violet emissions Feb 13, 2023 Issued
Array ( [id] => 19887018 [patent_doc_number] => 12272751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Negative capacitance transistor with a diffusion blocking layer [patent_app_type] => utility [patent_app_number] => 18/168417 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168417 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168417
Negative capacitance transistor with a diffusion blocking layer Feb 12, 2023 Issued
Array ( [id] => 18439982 [patent_doc_number] => 20230187277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => Method and IC Design with Non-Linear Power Rails [patent_app_type] => utility [patent_app_number] => 18/162841 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162841
Method and IC design with non-linear power rails Jan 31, 2023 Issued
Array ( [id] => 18424081 [patent_doc_number] => 20230178545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING VERTICAL ROUTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/103210 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103210
Semiconductor device including vertical routing structure and method for manufacturing the same Jan 29, 2023 Issued
Array ( [id] => 19524100 [patent_doc_number] => 12125840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Non-transitory computer-readable medium, integrated circuit device and method [patent_app_type] => utility [patent_app_number] => 18/156605 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 14233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156605
Non-transitory computer-readable medium, integrated circuit device and method Jan 18, 2023 Issued
Array ( [id] => 18379760 [patent_doc_number] => 20230154849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => LAYOUTS FOR CONDUCTIVE LAYERS IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/156086 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156086
Layouts for conductive layers in integrated circuits Jan 17, 2023 Issued
Array ( [id] => 19553826 [patent_doc_number] => 12137548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Four CPP wide memory cell with buried power grid, and method of fabricating same [patent_app_type] => utility [patent_app_number] => 18/155932 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155932
Four CPP wide memory cell with buried power grid, and method of fabricating same Jan 17, 2023 Issued
Array ( [id] => 19063218 [patent_doc_number] => 11942470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/155536 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 23572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155536
Semiconductor device and method for manufacturing the same Jan 16, 2023 Issued
Array ( [id] => 20161341 [patent_doc_number] => 12387976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings [patent_app_type] => utility [patent_app_number] => 18/151662 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 142 [patent_figures_cnt] => 228 [patent_no_of_words] => 57333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151662
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings Jan 8, 2023 Issued
Array ( [id] => 19765691 [patent_doc_number] => 12223989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/151994 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151994
Semiconductor device and method for fabricating the same Jan 8, 2023 Issued
Array ( [id] => 18680016 [patent_doc_number] => 20230317674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD HAVING HIGH-KAPPA BONDING LAYER [patent_app_type] => utility [patent_app_number] => 18/151160 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151160
SEMICONDUCTOR DEVICE AND METHOD HAVING HIGH-KAPPA BONDING LAYER Jan 5, 2023 Pending
Array ( [id] => 18945661 [patent_doc_number] => 20240040800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => FERROELECTRIC MEMORY DEVICE WITH BLOCKING LAYER [patent_app_type] => utility [patent_app_number] => 18/150289 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150289
Ferroelectric memory device with blocking layer Jan 4, 2023 Issued
Array ( [id] => 18882937 [patent_doc_number] => 20240006306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/149711 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149711
Semiconductor structure and manufacturing method thereof Jan 3, 2023 Issued
Array ( [id] => 18361864 [patent_doc_number] => 20230143455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => 3D NAND FLASH MEMORY DEVICES, AND RELATED ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/149318 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149318
3D NAND flash memory devices, and related electronic systems Jan 2, 2023 Issued
Array ( [id] => 19342728 [patent_doc_number] => 12052936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Superconductor-semiconductor Josephson junction [patent_app_type] => utility [patent_app_number] => 18/148145 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5035 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148145
Superconductor-semiconductor Josephson junction Dec 28, 2022 Issued
Array ( [id] => 18473179 [patent_doc_number] => 20230207467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => INTERCONNECTOR AND ELECTRONIC APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/145490 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145490
Interconnector and electronic apparatus including the same Dec 21, 2022 Issued
Array ( [id] => 19294626 [patent_doc_number] => 12033991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Package-on-package (PoP) semiconductor package and electronic system including the same [patent_app_type] => utility [patent_app_number] => 18/086727 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086727
Package-on-package (PoP) semiconductor package and electronic system including the same Dec 21, 2022 Issued
Array ( [id] => 19269539 [patent_doc_number] => 20240213243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => FORK SHEET DEVICE WITH WRAPPED SOURCE AND DRAIN CONTACT TO PREVENT NFET TO PFET CONTACT SHORTAGE IN A TIGHT SPACE [patent_app_type] => utility [patent_app_number] => 18/145003 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145003
Fork sheet device with wrapped source and drain contact to prevent NFET to PFET contact shortage in a tight space Dec 20, 2022 Issued
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