Robert A. Rose

Array ( [id] => 9065079 [patent_doc_number] => 20130256835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR' [patent_app_type] => utility [patent_app_number] => 13/434964 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8474410 [patent_doc_number] => 20120273816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'SEMICONDUCTOR OPTICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/434230 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8469720 [patent_doc_number] => 08298897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Asymmetric channel MOSFET' [patent_app_type] => utility [patent_app_number] => 13/428061 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 12699 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8289894 [patent_doc_number] => 20120178214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE FABRICATED USING PARTIAL ETCHING PROCESS' [patent_app_type] => utility [patent_app_number] => 13/426100 [patent_app_country] => US [patent_app_date] => 2012-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4295 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13426100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9051292 [patent_doc_number] => 20130249006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SELECTIVELY RAISED SOURCE/DRAIN TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/424787 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8283317 [patent_doc_number] => 08217422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Semiconductor devices with gate-source ESD diode and gate-drain clamp diode' [patent_app_type] => utility [patent_app_number] => 13/416597 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4807 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9291845 [patent_doc_number] => 20140035478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/002211 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16217 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14002211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9195213 [patent_doc_number] => 20130334528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR THE SAME, AND DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/001909 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7507 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8227955 [patent_doc_number] => 20120142162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/370590 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3191 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8643182 [patent_doc_number] => 08368170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Reducing device performance drift caused by large spacings between active regions' [patent_app_type] => utility [patent_app_number] => 13/367103 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4752 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13367103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8871113 [patent_doc_number] => 08466492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-18 [patent_title] => 'Semiconductor device with edge termination structure' [patent_app_type] => utility [patent_app_number] => 13/362005 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8073 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8196041 [patent_doc_number] => 20120121114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'HEARING INSTRUMENT WITH LINEARIZED OUTPUT STAGE' [patent_app_type] => utility [patent_app_number] => 13/359102 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2924 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20120121114.pdf [firstpage_image] =>[orig_patent_app_number] => 13359102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8191342 [patent_doc_number] => 20120118477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'STACKING APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUIT ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/359155 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8712 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20120118477.pdf [firstpage_image] =>[orig_patent_app_number] => 13359155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8846745 [patent_doc_number] => 08455931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Package configurations for low EMI circuits' [patent_app_type] => utility [patent_app_number] => 13/355885 [patent_app_country] => US [patent_app_date] => 2012-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7439 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13355885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8457943 [patent_doc_number] => 08293609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method of manufacturing a transistor device having asymmetric embedded strain elements' [patent_app_type] => utility [patent_app_number] => 13/355221 [patent_app_country] => US [patent_app_date] => 2012-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6036 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13355221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8625489 [patent_doc_number] => 08357985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Bipolar transistor with guard region' [patent_app_type] => utility [patent_app_number] => 13/350582 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13350582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8642485 [patent_doc_number] => 08367469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Chip-scale semiconductor die packaging method' [patent_app_type] => utility [patent_app_number] => 13/347543 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9075 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8172661 [patent_doc_number] => 20120108024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL' [patent_app_type] => utility [patent_app_number] => 13/345252 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2911 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20120108024.pdf [firstpage_image] =>[orig_patent_app_number] => 13345252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7815025 [patent_doc_number] => 20120061645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'OPTOELECTRONIC DEVICE BASED ON NON-POLAR AND SEMI-POLAR ALUMINUM INDIUM NITRIDE AND ALUMINUM INDIUM GALLIUM NITRIDE ALLOYS' [patent_app_type] => utility [patent_app_number] => 13/300977 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7222 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061645.pdf [firstpage_image] =>[orig_patent_app_number] => 13300977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9259844 [patent_doc_number] => 20130341773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'ENCAPSULATION OF AN MEMS COMPONENT AND A METHOD FOR PRODUCING SAID COMPONENT' [patent_app_type] => utility [patent_app_number] => 13/976420 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976420 [rel_patent_id] =>[rel_patent_doc_number] =>)