Robert A. Rose

Array ( [id] => 7601433 [patent_doc_number] => 07385272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method and apparatus for removing electrons from CMOS sensor photodetectors' [patent_app_type] => utility [patent_app_number] => 11/713822 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 10245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/385/07385272.pdf [firstpage_image] =>[orig_patent_app_number] => 11713822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 232698 [patent_doc_number] => 07598123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Semiconductor component and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/681500 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 6331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598123.pdf [firstpage_image] =>[orig_patent_app_number] => 11681500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 349174 [patent_doc_number] => 07495292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate' [patent_app_type] => utility [patent_app_number] => 11/713160 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4584 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495292.pdf [firstpage_image] =>[orig_patent_app_number] => 11713160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4698158 [patent_doc_number] => 20080220342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'METHODS OF FABRICATING OPTICAL PACKAGES, SYSTEMS COMPRISING THE SAME, AND THEIR USES' [patent_app_type] => utility [patent_app_number] => 11/713010 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4685 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20080220342.pdf [firstpage_image] =>[orig_patent_app_number] => 11713010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4673309 [patent_doc_number] => 20080210937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Hetero-Crystalline Structure and Method of Making Same' [patent_app_type] => utility [patent_app_number] => 11/681080 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20080210937.pdf [firstpage_image] =>[orig_patent_app_number] => 11681080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4701833 [patent_doc_number] => 20080061355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Method of reducing memory cell size for floating gate NAND flash' [patent_app_type] => utility [patent_app_number] => 11/713780 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061355.pdf [firstpage_image] =>[orig_patent_app_number] => 11713780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4673432 [patent_doc_number] => 20080211060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'ANTI-FUSE WHICH WILL NOT GENERATE A NON-LINEAR CURRENT AFTER BEING BLOWN AND OTP MEMORY CELL UTILIZING THE ANTI-FUSE' [patent_app_type] => utility [patent_app_number] => 11/680630 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4060 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211060.pdf [firstpage_image] =>[orig_patent_app_number] => 11680630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307778 [patent_doc_number] => 07531851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-12 [patent_title] => 'Electronic device with reduced interface charge between epitaxially grown layers and a method for making the same' [patent_app_type] => utility [patent_app_number] => 11/713070 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6489 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531851.pdf [firstpage_image] =>[orig_patent_app_number] => 11713070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7595217 [patent_doc_number] => 07626244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Stressed dielectric devices and methods of fabricating same' [patent_app_type] => utility [patent_app_number] => 11/679880 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 3606 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626244.pdf [firstpage_image] =>[orig_patent_app_number] => 11679880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4698086 [patent_doc_number] => 20080220270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Fabricating Tall Micro Structures' [patent_app_type] => utility [patent_app_number] => 11/680600 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5411 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20080220270.pdf [firstpage_image] =>[orig_patent_app_number] => 11680600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5019496 [patent_doc_number] => 20070145462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Low tunnel barrier insulators' [patent_app_type] => utility [patent_app_number] => 11/708438 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10785 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145462.pdf [firstpage_image] =>[orig_patent_app_number] => 11708438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4829100 [patent_doc_number] => 20080128681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'VERTICAL ORGANIC TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/675140 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5349 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128681.pdf [firstpage_image] =>[orig_patent_app_number] => 11675140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 163170 [patent_doc_number] => 07671412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Method and device for controlling temperature of a substrate using an internal temperature control device' [patent_app_type] => utility [patent_app_number] => 11/675210 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5449 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671412.pdf [firstpage_image] =>[orig_patent_app_number] => 11675210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5002578 [patent_doc_number] => 20070200144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'METHOD FOR PRODUCING PARTIAL SOI STRUCTURES COMPRISING ZONES CONNECTING A SUPERFICIAL LAYER AND A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/673820 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4099 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20070200144.pdf [firstpage_image] =>[orig_patent_app_number] => 11673820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5413 [patent_doc_number] => 07812373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'MuGFET array layout' [patent_app_type] => utility [patent_app_number] => 11/674060 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2341 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812373.pdf [firstpage_image] =>[orig_patent_app_number] => 11674060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5116820 [patent_doc_number] => 20070138534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators' [patent_app_type] => utility [patent_app_number] => 11/704458 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10783 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138534.pdf [firstpage_image] =>[orig_patent_app_number] => 11704458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5066741 [patent_doc_number] => 20070187842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'PRINTED CIRCUIT, METHOD OF MANUFACTURING THE PRINTED CIRCUIT, PRINTED CIRCUIT/ELECTRONIC ELEMENT ASSEMBLY, AND METHOD OF MANUFACTURING THE PRINTED CIRCUIT/ELECTRONIC ELEMENT ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 11/673230 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4568 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187842.pdf [firstpage_image] =>[orig_patent_app_number] => 11673230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5236643 [patent_doc_number] => 20070128800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'USE OF CHLORINE TO FABRICATE TRENCH DIELECTRIC IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/671740 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2075 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128800.pdf [firstpage_image] =>[orig_patent_app_number] => 11671740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4953764 [patent_doc_number] => 20080186788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'ELECTRICAL FUSE AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 11/670770 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3488 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186788.pdf [firstpage_image] =>[orig_patent_app_number] => 11670770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4477099 [patent_doc_number] => 07868388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Embedded memory in a CMOS circuit and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 11/669850 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8573 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/868/07868388.pdf [firstpage_image] =>[orig_patent_app_number] => 11669850 [rel_patent_id] =>[rel_patent_doc_number] =>)