
Robert A. Sorey
Examiner (ID: 16547, Phone: (571)270-3606 , Office: P/3626 )
| Most Active Art Unit | 3626 |
| Art Unit(s) | 3626, 3682 |
| Total Applications | 514 |
| Issued Applications | 231 |
| Pending Applications | 61 |
| Abandoned Applications | 235 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11607912
[patent_doc_number] => 20170125215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'METHODS FOR THIN FILM MATERIAL DEPOSITION USING REACTIVE PLASMA-FREE PHYSICAL VAPOR DEPOSITION'
[patent_app_type] => utility
[patent_app_number] => 14/986168
[patent_app_country] => US
[patent_app_date] => 2015-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4461
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14986168
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/986168 | Methods for thin film material deposition using reactive plasma-free physical vapor deposition | Dec 30, 2015 | Issued |
Array
(
[id] => 10772328
[patent_doc_number] => 20160118484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-28
[patent_title] => 'Bipolar Transistor with Enclosed Sub Areas and a Method for Manufacturing Such a Bipolar Transistor'
[patent_app_type] => utility
[patent_app_number] => 14/984907
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7580
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984907
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/984907 | Bipolar Transistor with Enclosed Sub Areas and a Method for Manufacturing Such a Bipolar Transistor | Dec 29, 2015 | Abandoned |
Array
(
[id] => 12346269
[patent_doc_number] => 09950924
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-24
[patent_title] => Methods and structures of integrated MEMS-CMOS devices
[patent_app_type] => utility
[patent_app_number] => 14/985388
[patent_app_country] => US
[patent_app_date] => 2015-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 62
[patent_no_of_words] => 9446
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14985388
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/985388 | Methods and structures of integrated MEMS-CMOS devices | Dec 29, 2015 | Issued |
Array
(
[id] => 11718436
[patent_doc_number] => 20170186935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-29
[patent_title] => 'Low Temperature Deposition of Silicon Containing Layers in Superconducting Circuits'
[patent_app_type] => utility
[patent_app_number] => 14/982307
[patent_app_country] => US
[patent_app_date] => 2015-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3891
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982307
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/982307 | Low Temperature Deposition of Silicon Containing Layers in Superconducting Circuits | Dec 28, 2015 | Abandoned |
Array
(
[id] => 10993109
[patent_doc_number] => 20160190056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-30
[patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANISM AND METHOD OF MANUFACTURE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/980292
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980292
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980292 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANISM AND METHOD OF MANUFACTURE THEREOF | Dec 27, 2015 | Abandoned |
Array
(
[id] => 11718299
[patent_doc_number] => 20170186798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-29
[patent_title] => 'STACKED SPAD IMAGE SENSOR'
[patent_app_type] => utility
[patent_app_number] => 14/980386
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6080
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980386
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980386 | Stacked SPAD image sensor | Dec 27, 2015 | Issued |
Array
(
[id] => 12573894
[patent_doc_number] => 10020224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-10
[patent_title] => Self-aligned via forming to conductive line and related wiring structure
[patent_app_type] => utility
[patent_app_number] => 14/980320
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2811
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980320
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980320 | Self-aligned via forming to conductive line and related wiring structure | Dec 27, 2015 | Issued |
Array
(
[id] => 11718152
[patent_doc_number] => 20170186652
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-29
[patent_title] => 'METHOD FOR PREVENTING DISHING DURING THE MANUFACTURE OF SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/980779
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4349
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980779
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980779 | Method for preventing dishing during the manufacture of semiconductor devices | Dec 27, 2015 | Issued |
Array
(
[id] => 13293583
[patent_doc_number] => 10157992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-18
[patent_title] => Nanowire device with reduced parasitics
[patent_app_type] => utility
[patent_app_number] => 14/980850
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2964
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980850
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980850 | Nanowire device with reduced parasitics | Dec 27, 2015 | Issued |
Array
(
[id] => 11460019
[patent_doc_number] => 20170053925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'ANTIFUSE-TYPE ONE TIME PROGRAMMING MEMORY CELL AND ARRAY STRUCTURE WITH SAME'
[patent_app_type] => utility
[patent_app_number] => 14/980875
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5323
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980875
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980875 | Antifuse-type one time programming memory cell and array structure with same | Dec 27, 2015 | Issued |
Array
(
[id] => 13288963
[patent_doc_number] => 10155656
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-18
[patent_title] => Inter-poly connection for parasitic capacitor and die size improvement
[patent_app_type] => utility
[patent_app_number] => 14/980297
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5299
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980297
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980297 | Inter-poly connection for parasitic capacitor and die size improvement | Dec 27, 2015 | Issued |
Array
(
[id] => 11404895
[patent_doc_number] => 20170025433
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'SEMICONDUCTOR DEVICE WITH HIGH INTEGRATION'
[patent_app_type] => utility
[patent_app_number] => 14/980244
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9899
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980244
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980244 | Semiconductor device with high integration | Dec 27, 2015 | Issued |
Array
(
[id] => 12019703
[patent_doc_number] => 09812412
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'Chip part having passive elements on a common substrate'
[patent_app_type] => utility
[patent_app_number] => 14/980404
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
[patent_figures_cnt] => 64
[patent_no_of_words] => 30046
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980404
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/980404 | Chip part having passive elements on a common substrate | Dec 27, 2015 | Issued |
Array
(
[id] => 13159727
[patent_doc_number] => 10096599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-09
[patent_title] => Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process
[patent_app_type] => utility
[patent_app_number] => 14/977367
[patent_app_country] => US
[patent_app_date] => 2015-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 39
[patent_no_of_words] => 10842
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 603
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977367
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/977367 | Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process | Dec 20, 2015 | Issued |
Array
(
[id] => 10755472
[patent_doc_number] => 20160101624
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-14
[patent_title] => 'METHOD OF MANUFACTURING AN INK-JET PRINTHEAD'
[patent_app_type] => utility
[patent_app_number] => 14/970849
[patent_app_country] => US
[patent_app_date] => 2015-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7075
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970849
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/970849 | Method of manufacturing an ink-jet printhead having frusto-pyramidal shaped nozzles | Dec 15, 2015 | Issued |
Array
(
[id] => 11014400
[patent_doc_number] => 20160211353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'METHOD OF MANUFACTURING OXIDE THIN FILM TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 14/966125
[patent_app_country] => US
[patent_app_date] => 2015-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5866
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966125
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/966125 | METHOD OF MANUFACTURING OXIDE THIN FILM TRANSISTOR | Dec 10, 2015 | Abandoned |
Array
(
[id] => 10826363
[patent_doc_number] => 20160172532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/965894
[patent_app_country] => US
[patent_app_date] => 2015-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17076
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965894
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/965894 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE | Dec 9, 2015 | Abandoned |
Array
(
[id] => 11599856
[patent_doc_number] => 09647033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Methods of manufacturing magnetic memory device having a magnetic tunnel junction pattern'
[patent_app_type] => utility
[patent_app_number] => 14/965386
[patent_app_country] => US
[patent_app_date] => 2015-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 25
[patent_no_of_words] => 9744
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965386
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/965386 | Methods of manufacturing magnetic memory device having a magnetic tunnel junction pattern | Dec 9, 2015 | Issued |
Array
(
[id] => 11431980
[patent_doc_number] => 09570304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-14
[patent_title] => 'Method of forming fine patterns in an anti-reflection layer for use as a patterning hard mask'
[patent_app_type] => utility
[patent_app_number] => 14/965255
[patent_app_country] => US
[patent_app_date] => 2015-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3936
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965255
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/965255 | Method of forming fine patterns in an anti-reflection layer for use as a patterning hard mask | Dec 9, 2015 | Issued |
Array
(
[id] => 11483296
[patent_doc_number] => 09589850
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-03-07
[patent_title] => 'Method for controlled recessing of materials in cavities in IC devices'
[patent_app_type] => utility
[patent_app_number] => 14/964746
[patent_app_country] => US
[patent_app_date] => 2015-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 2950
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964746
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/964746 | Method for controlled recessing of materials in cavities in IC devices | Dec 9, 2015 | Issued |