Robert E. Fennema

Array ( [id] => 87658 [patent_doc_number] => 07743232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Multiple-core processor with hierarchical microcode store' [patent_app_type] => utility [patent_app_number] => 11/779642 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743232.pdf [firstpage_image] =>[orig_patent_app_number] => 11779642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4472239 [patent_doc_number] => 07937574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Precise counter hardware for microcode loops' [patent_app_type] => utility [patent_app_number] => 11/778936 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937574.pdf [firstpage_image] =>[orig_patent_app_number] => 11778936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4659329 [patent_doc_number] => 20080028191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'INSTRUCTION SET AND INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/777763 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7421 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028191.pdf [firstpage_image] =>[orig_patent_app_number] => 11777763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9282914 [patent_doc_number] => 20140032882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'MODIFICATION OF FUNCTIONALITY IN EXECUTABLE CODE' [patent_app_type] => utility [patent_app_number] => 11/777460 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11777460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4804739 [patent_doc_number] => 20080016328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'INFORMATION PROCESSING EQUIPMENT AND METHOD OF CHANGING PROCESSOR FUNCTION' [patent_app_type] => utility [patent_app_number] => 11/776602 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7469 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016328.pdf [firstpage_image] =>[orig_patent_app_number] => 11776602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4653321 [patent_doc_number] => 20080040578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'MULTI-THREAD PROCESSOR WITH MULTIPLE PROGRAM COUNTERS' [patent_app_type] => utility [patent_app_number] => 11/775152 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6056 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040578.pdf [firstpage_image] =>[orig_patent_app_number] => 11775152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 37522 [patent_doc_number] => 07793073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method and apparatus for indirectly addressed vector load-add-store across multi-processors' [patent_app_type] => utility [patent_app_number] => 11/771931 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10734 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793073.pdf [firstpage_image] =>[orig_patent_app_number] => 11771931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5200723 [patent_doc_number] => 20070300041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Method for processing streaming data in a multiprocessor system' [patent_app_type] => utility [patent_app_number] => 11/821065 [patent_app_country] => US [patent_app_date] => 2007-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2845 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300041.pdf [firstpage_image] =>[orig_patent_app_number] => 11821065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4854531 [patent_doc_number] => 20080320274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Age matrix for queue dispatch order' [patent_app_type] => utility [patent_app_number] => 11/820350 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5128 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320274.pdf [firstpage_image] =>[orig_patent_app_number] => 11820350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9707322 [patent_doc_number] => 08832416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Method and apparatus for instruction completion stall identification in an information handling system' [patent_app_type] => utility [patent_app_number] => 11/753005 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6012 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11753005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4780757 [patent_doc_number] => 20080288756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => '\"OR\" BIT MATRIX MULTIPLY VECTOR INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 11/750928 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1979 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288756.pdf [firstpage_image] =>[orig_patent_app_number] => 11750928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4641942 [patent_doc_number] => 08019976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Memory-hazard detection and avoidance instructions for vector processing' [patent_app_type] => utility [patent_app_number] => 11/803576 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7097 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019976.pdf [firstpage_image] =>[orig_patent_app_number] => 11803576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4796807 [patent_doc_number] => 20080008393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/748367 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12768 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20080008393.pdf [firstpage_image] =>[orig_patent_app_number] => 11748367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4549236 [patent_doc_number] => 07925860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-12 [patent_title] => 'Maximized memory throughput using cooperative thread arrays' [patent_app_type] => utility [patent_app_number] => 11/748298 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11150 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925860.pdf [firstpage_image] =>[orig_patent_app_number] => 11748298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4841577 [patent_doc_number] => 20080282063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'METHODS AND APPARATUS FOR LATENCY CONTROL IN A MULTIPROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/746408 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282063.pdf [firstpage_image] =>[orig_patent_app_number] => 11746408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 163314 [patent_doc_number] => 07676653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Compact instruction set encoding' [patent_app_type] => utility [patent_app_number] => 11/797968 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9478 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676653.pdf [firstpage_image] =>[orig_patent_app_number] => 11797968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4841586 [patent_doc_number] => 20080282072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table' [patent_app_type] => utility [patent_app_number] => 11/745657 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282072.pdf [firstpage_image] =>[orig_patent_app_number] => 11745657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722373 [patent_doc_number] => 20080244244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'PARALLEL INSTRUCTION PROCESSING AND OPERAND INTEGRITY VERIFICATION' [patent_app_type] => utility [patent_app_number] => 11/694870 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244244.pdf [firstpage_image] =>[orig_patent_app_number] => 11694870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722343 [patent_doc_number] => 20080244221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/694322 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244221.pdf [firstpage_image] =>[orig_patent_app_number] => 11694322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722350 [patent_doc_number] => 20080244226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Thread migration control based on prediction of migration overhead' [patent_app_type] => utility [patent_app_number] => 11/731276 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3406 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244226.pdf [firstpage_image] =>[orig_patent_app_number] => 11731276 [rel_patent_id] =>[rel_patent_doc_number] =>)