Search

Robert E. Fennema

Supervisory Patent Examiner (ID: 11059, Phone: (571)272-2748 , Office: P/2126 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2117, 2124, 2126, 2118
Total Applications
376
Issued Applications
186
Pending Applications
14
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4722362 [patent_doc_number] => 20080244234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'System and Method for Executing Instructions Prior to an Execution Stage in a Processor' [patent_app_type] => utility [patent_app_number] => 11/692685 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7790 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244234.pdf [firstpage_image] =>[orig_patent_app_number] => 11692685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692685
System and method for executing instructions prior to an execution stage in a processor Mar 27, 2007 Issued
Array ( [id] => 7690014 [patent_doc_number] => 20070234019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Processor apparatus and complex condition processing method' [patent_app_type] => utility [patent_app_number] => 11/723623 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9518 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234019.pdf [firstpage_image] =>[orig_patent_app_number] => 11723623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723623
Processor apparatus and complex condition processing method Mar 20, 2007 Abandoned
Array ( [id] => 8285674 [patent_doc_number] => 08219786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Request coalescing for instruction streams' [patent_app_type] => utility [patent_app_number] => 11/688480 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11688480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688480
Request coalescing for instruction streams Mar 19, 2007 Issued
Array ( [id] => 4815215 [patent_doc_number] => 20080195846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Distributed Dispatch with Concurrent, Out-of-Order Dispatch' [patent_app_type] => utility [patent_app_number] => 11/674562 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195846.pdf [firstpage_image] =>[orig_patent_app_number] => 11674562 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/674562
Distributed dispatch with concurrent, out-of-order dispatch Feb 12, 2007 Issued
Array ( [id] => 5065153 [patent_doc_number] => 20070226795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'VIRTUAL CORES AND HARDWARE-SUPPORTED HYPERVISOR INTEGRATED CIRCUITS, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 11/671752 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 69926 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226795.pdf [firstpage_image] =>[orig_patent_app_number] => 11671752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671752
VIRTUAL CORES AND HARDWARE-SUPPORTED HYPERVISOR INTEGRATED CIRCUITS, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE Feb 5, 2007 Abandoned
Array ( [id] => 8010819 [patent_doc_number] => 08086827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Mechanism for irrevocable transactions' [patent_app_type] => utility [patent_app_number] => 11/648485 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7610 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086827.pdf [firstpage_image] =>[orig_patent_app_number] => 11648485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648485
Mechanism for irrevocable transactions Dec 27, 2006 Issued
Array ( [id] => 4693853 [patent_doc_number] => 20080086624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Latch to block short path violation' [patent_app_type] => utility [patent_app_number] => 11/638703 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4006 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086624.pdf [firstpage_image] =>[orig_patent_app_number] => 11638703 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/638703
Latch to block short path violation Dec 13, 2006 Issued
Array ( [id] => 4869030 [patent_doc_number] => 20080148089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Single Shared Instruction Predecoder for Supporting Multiple Processors' [patent_app_type] => utility [patent_app_number] => 11/610110 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9469 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148089.pdf [firstpage_image] =>[orig_patent_app_number] => 11610110 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610110
Single shared instruction predecoder for supporting multiple processors Dec 12, 2006 Issued
Array ( [id] => 4868961 [patent_doc_number] => 20080148020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Low Cost Persistent Instruction Predecoded Issue and Dispatcher' [patent_app_type] => utility [patent_app_number] => 11/610214 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148020.pdf [firstpage_image] =>[orig_patent_app_number] => 11610214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610214
Low Cost Persistent Instruction Predecoded Issue and Dispatcher Dec 12, 2006 Abandoned
Array ( [id] => 4787923 [patent_doc_number] => 20080141252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Cascaded Delayed Execution Pipeline' [patent_app_type] => utility [patent_app_number] => 11/608988 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141252.pdf [firstpage_image] =>[orig_patent_app_number] => 11608988 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608988
Cascaded Delayed Execution Pipeline Dec 10, 2006 Abandoned
Array ( [id] => 4787673 [patent_doc_number] => 20080141002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'INSTRUCTION PIPELINE MONITORING DEVICE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/608697 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8024 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141002.pdf [firstpage_image] =>[orig_patent_app_number] => 11608697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608697
INSTRUCTION PIPELINE MONITORING DEVICE AND METHOD THEREOF Dec 7, 2006 Abandoned
Array ( [id] => 8799485 [patent_doc_number] => 08438370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-07 [patent_title] => 'Processing of loops with internal data dependencies using a parallel processor' [patent_app_type] => utility [patent_app_number] => 11/608762 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11608762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608762
Processing of loops with internal data dependencies using a parallel processor Dec 7, 2006 Issued
Array ( [id] => 4787657 [patent_doc_number] => 20080140986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'METHOD FOR ACCESSING TARGET REGISTER OF REGISTERS AND APPARATUS THEREOF' [patent_app_type] => utility [patent_app_number] => 11/608247 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3142 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140986.pdf [firstpage_image] =>[orig_patent_app_number] => 11608247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608247
METHOD FOR ACCESSING TARGET REGISTER OF REGISTERS AND APPARATUS THEREOF Dec 7, 2006 Abandoned
Array ( [id] => 5024928 [patent_doc_number] => 20070150895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Methods and apparatus for multi-core processing with dedicated thread management' [patent_app_type] => utility [patent_app_number] => 11/634512 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3488 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150895.pdf [firstpage_image] =>[orig_patent_app_number] => 11634512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/634512
Methods and apparatus for multi-core processing with dedicated thread management Dec 5, 2006 Abandoned
Array ( [id] => 9029611 [patent_doc_number] => 08539207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Lattice-based computations on a parallel processor' [patent_app_type] => utility [patent_app_number] => 11/556683 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11556683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556683
Lattice-based computations on a parallel processor Nov 2, 2006 Issued
Array ( [id] => 4923702 [patent_doc_number] => 20080072019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Technique to clear bogus instructions from a processor pipeline' [patent_app_type] => utility [patent_app_number] => 11/523930 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5042 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072019.pdf [firstpage_image] =>[orig_patent_app_number] => 11523930 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/523930
Technique to clear bogus instructions from a processor pipeline Sep 18, 2006 Abandoned
Array ( [id] => 6363441 [patent_doc_number] => 20100250853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Prefetch engine based translation prefetching' [patent_app_type] => utility [patent_app_number] => 11/482222 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250853.pdf [firstpage_image] =>[orig_patent_app_number] => 11482222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482222
Prefetch engine based translation prefetching Jul 6, 2006 Issued
Array ( [id] => 7972121 [patent_doc_number] => 07941639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Protection of the execution of a program' [patent_app_type] => utility [patent_app_number] => 11/481432 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1945 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941639.pdf [firstpage_image] =>[orig_patent_app_number] => 11481432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/481432
Protection of the execution of a program Jul 4, 2006 Issued
Array ( [id] => 27304 [patent_doc_number] => 07802075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Synchronized high-assurance circuits' [patent_app_type] => utility [patent_app_number] => 11/428516 [patent_app_country] => US [patent_app_date] => 2006-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3183 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802075.pdf [firstpage_image] =>[orig_patent_app_number] => 11428516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428516
Synchronized high-assurance circuits Jul 2, 2006 Issued
Array ( [id] => 4934760 [patent_doc_number] => 20080005535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Speculatively scheduling micro-operations after allocation' [patent_app_type] => utility [patent_app_number] => 11/479746 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4073 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005535.pdf [firstpage_image] =>[orig_patent_app_number] => 11479746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479746
Speculatively scheduling micro-operations after allocation Jun 29, 2006 Issued
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