
Robert E. Fennema
Supervisory Patent Examiner (ID: 11059, Phone: (571)272-2748 , Office: P/2126 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2117, 2124, 2126, 2118 |
| Total Applications | 376 |
| Issued Applications | 186 |
| Pending Applications | 14 |
| Abandoned Applications | 176 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4722362
[patent_doc_number] => 20080244234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'System and Method for Executing Instructions Prior to an Execution Stage in a Processor'
[patent_app_type] => utility
[patent_app_number] => 11/692685
[patent_app_country] => US
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[pdf_file] => publications/A1/0244/20080244234.pdf
[firstpage_image] =>[orig_patent_app_number] => 11692685
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/692685 | System and method for executing instructions prior to an execution stage in a processor | Mar 27, 2007 | Issued |
Array
(
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[patent_doc_number] => 20070234019
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[patent_issue_date] => 2007-10-04
[patent_title] => 'Processor apparatus and complex condition processing method'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2007-03-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/723623 | Processor apparatus and complex condition processing method | Mar 20, 2007 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688480 | Request coalescing for instruction streams | Mar 19, 2007 | Issued |
Array
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[patent_issue_date] => 2008-08-14
[patent_title] => 'Distributed Dispatch with Concurrent, Out-of-Order Dispatch'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/674562 | Distributed dispatch with concurrent, out-of-order dispatch | Feb 12, 2007 | Issued |
Array
(
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[patent_title] => 'VIRTUAL CORES AND HARDWARE-SUPPORTED HYPERVISOR INTEGRATED CIRCUITS, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE'
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Array
(
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[patent_issue_date] => 2011-12-27
[patent_title] => 'Mechanism for irrevocable transactions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648485 | Mechanism for irrevocable transactions | Dec 27, 2006 | Issued |
Array
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[patent_title] => 'Latch to block short path violation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/638703 | Latch to block short path violation | Dec 13, 2006 | Issued |
Array
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[id] => 4869030
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[patent_issue_date] => 2008-06-19
[patent_title] => 'Single Shared Instruction Predecoder for Supporting Multiple Processors'
[patent_app_type] => utility
[patent_app_number] => 11/610110
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[firstpage_image] =>[orig_patent_app_number] => 11610110
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Array
(
[id] => 4868961
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/610214 | Low Cost Persistent Instruction Predecoded Issue and Dispatcher | Dec 12, 2006 | Abandoned |
Array
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Array
(
[id] => 4787673
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Array
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Array
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Array
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Array
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Array
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[id] => 4923702
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Array
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Array
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Array
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