Search

Robert E. Fennema

Supervisory Patent Examiner (ID: 7795, Phone: (571)272-2748 , Office: P/2126 )

Most Active Art Unit
2183
Art Unit(s)
2124, 2183, 2117, 2126, 2118
Total Applications
376
Issued Applications
185
Pending Applications
17
Abandoned Applications
174

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5665894 [patent_doc_number] => 20060171244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'CHIP LAYOUT FOR MULTIPLE CPU CORE MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 10/906108 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20060171244.pdf [firstpage_image] =>[orig_patent_app_number] => 10906108 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906108
CHIP LAYOUT FOR MULTIPLE CPU CORE MICROPROCESSOR Feb 2, 2005 Abandoned
Array ( [id] => 358498 [patent_doc_number] => 07490227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-10 [patent_title] => 'Method and system to recreate instruction and data traces in an embedded processor' [patent_app_type] => utility [patent_app_number] => 10/930437 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2534 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490227.pdf [firstpage_image] =>[orig_patent_app_number] => 10930437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930437
Method and system to recreate instruction and data traces in an embedded processor Aug 30, 2004 Issued
Array ( [id] => 7009030 [patent_doc_number] => 20050062746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Signal-processing apparatus and electronic apparatus using same' [patent_app_type] => utility [patent_app_number] => 10/919238 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11908 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062746.pdf [firstpage_image] =>[orig_patent_app_number] => 10919238 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/919238
Signal-processing apparatus and electronic apparatus using same Aug 16, 2004 Abandoned
Array ( [id] => 7013926 [patent_doc_number] => 20050066354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Circuit for restricting data access' [patent_app_type] => utility [patent_app_number] => 10/917253 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4407 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066354.pdf [firstpage_image] =>[orig_patent_app_number] => 10917253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917253
Circuit for restricting data access Aug 11, 2004 Abandoned
Array ( [id] => 5822058 [patent_doc_number] => 20060026371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method and apparatus for implementing memory order models with order vectors' [patent_app_type] => utility [patent_app_number] => 10/903675 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5050 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026371.pdf [firstpage_image] =>[orig_patent_app_number] => 10903675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/903675
Method and apparatus for implementing memory order models with order vectors Jul 29, 2004 Abandoned
Array ( [id] => 8804888 [patent_doc_number] => 08443171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Run-time updating of prediction hint instructions' [patent_app_type] => utility [patent_app_number] => 10/903155 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4284 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10903155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/903155
Run-time updating of prediction hint instructions Jul 29, 2004 Issued
Array ( [id] => 820023 [patent_doc_number] => 07412586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Switch memory architectures' [patent_app_type] => utility [patent_app_number] => 10/901102 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 11707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412586.pdf [firstpage_image] =>[orig_patent_app_number] => 10901102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901102
Switch memory architectures Jul 28, 2004 Issued
Array ( [id] => 7972133 [patent_doc_number] => 07941645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Isochronous pipelined processor with deterministic control' [patent_app_type] => utility [patent_app_number] => 10/901887 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11835 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941645.pdf [firstpage_image] =>[orig_patent_app_number] => 10901887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901887
Isochronous pipelined processor with deterministic control Jul 27, 2004 Issued
Array ( [id] => 7160325 [patent_doc_number] => 20050027969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Method for performing single instruction multiple data operations on packed data' [patent_app_type] => utility [patent_app_number] => 10/899193 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6252 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20050027969.pdf [firstpage_image] =>[orig_patent_app_number] => 10899193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899193
Method for performing single instruction multiple data operations on packed data Jul 25, 2004 Abandoned
Array ( [id] => 226813 [patent_doc_number] => 07606995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Allocating resources to partitions in a partitionable computer' [patent_app_type] => utility [patent_app_number] => 10/898590 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10149 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/606/07606995.pdf [firstpage_image] =>[orig_patent_app_number] => 10898590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898590
Allocating resources to partitions in a partitionable computer Jul 22, 2004 Issued
Array ( [id] => 7185550 [patent_doc_number] => 20050125638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Data shift operations' [patent_app_type] => utility [patent_app_number] => 10/889365 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 29330 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125638.pdf [firstpage_image] =>[orig_patent_app_number] => 10889365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889365
Data shift operations Jul 12, 2004 Abandoned
Array ( [id] => 6946656 [patent_doc_number] => 20050198473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Multiplexing operations in SIMD processing' [patent_app_type] => utility [patent_app_number] => 10/889366 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 28740 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198473.pdf [firstpage_image] =>[orig_patent_app_number] => 10889366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889366
Multiplexing operations in SIMD processing Jul 12, 2004 Abandoned
Array ( [id] => 7185531 [patent_doc_number] => 20050125636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Vector by scalar operations' [patent_app_type] => utility [patent_app_number] => 10/889316 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 28892 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125636.pdf [firstpage_image] =>[orig_patent_app_number] => 10889316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889316
Vector by scalar operations Jul 12, 2004 Abandoned
Array ( [id] => 7599782 [patent_doc_number] => 07546642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Latching processor state information' [patent_app_type] => utility [patent_app_number] => 10/887307 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8185 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546642.pdf [firstpage_image] =>[orig_patent_app_number] => 10887307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887307
Latching processor state information Jul 8, 2004 Issued
Array ( [id] => 7972127 [patent_doc_number] => 07941642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Method for selecting between divide instructions associated with respective threads in a multi-threaded processor' [patent_app_type] => utility [patent_app_number] => 10/881216 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9509 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941642.pdf [firstpage_image] =>[orig_patent_app_number] => 10881216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881216
Method for selecting between divide instructions associated with respective threads in a multi-threaded processor Jun 29, 2004 Issued
Array ( [id] => 8460865 [patent_doc_number] => 08296549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Overlapping command at one stage submitting method of dynamic cycle pipeline' [patent_app_type] => utility [patent_app_number] => 10/585016 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3137 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10585016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/585016
Overlapping command at one stage submitting method of dynamic cycle pipeline Jun 21, 2004 Issued
Array ( [id] => 254445 [patent_doc_number] => 07581088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-25 [patent_title] => 'Conditional execution using an efficient processor flag' [patent_app_type] => utility [patent_app_number] => 10/870810 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6383 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/581/07581088.pdf [firstpage_image] =>[orig_patent_app_number] => 10870810 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870810
Conditional execution using an efficient processor flag Jun 15, 2004 Issued
Array ( [id] => 7233041 [patent_doc_number] => 20050262311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Hierarchical processor architecture for video processing' [patent_app_type] => utility [patent_app_number] => 10/850095 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4363 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262311.pdf [firstpage_image] =>[orig_patent_app_number] => 10850095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/850095
Hierarchical processor architecture for video processing May 19, 2004 Abandoned
Array ( [id] => 7300403 [patent_doc_number] => 20040215940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Processor, compiling apparatus, and compile program recorded on a recording medium' [patent_app_type] => new [patent_app_number] => 10/846518 [patent_app_country] => US [patent_app_date] => 2004-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22331 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215940.pdf [firstpage_image] =>[orig_patent_app_number] => 10846518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/846518
Processor, compiling apparatus, and compile program recorded on a recording medium May 16, 2004 Abandoned
Array ( [id] => 8594829 [patent_doc_number] => 08352712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted' [patent_app_type] => utility [patent_app_number] => 10/840560 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7950 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10840560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840560
Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted May 5, 2004 Issued
Menu