
Robert E. Fennema
Supervisory Patent Examiner (ID: 7795, Phone: (571)272-2748 , Office: P/2126 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2124, 2183, 2117, 2126, 2118 |
| Total Applications | 376 |
| Issued Applications | 185 |
| Pending Applications | 17 |
| Abandoned Applications | 174 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5665894
[patent_doc_number] => 20060171244
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[patent_issue_date] => 2006-08-03
[patent_title] => 'CHIP LAYOUT FOR MULTIPLE CPU CORE MICROPROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 10/906108
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906108 | CHIP LAYOUT FOR MULTIPLE CPU CORE MICROPROCESSOR | Feb 2, 2005 | Abandoned |
Array
(
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[patent_doc_number] => 07490227
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[patent_kind] => B1
[patent_issue_date] => 2009-02-10
[patent_title] => 'Method and system to recreate instruction and data traces in an embedded processor'
[patent_app_type] => utility
[patent_app_number] => 10/930437
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Array
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[patent_issue_date] => 2005-03-24
[patent_title] => 'Signal-processing apparatus and electronic apparatus using same'
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Array
(
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[patent_issue_date] => 2005-03-24
[patent_title] => 'Circuit for restricting data access'
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Array
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[patent_title] => 'Method and apparatus for implementing memory order models with order vectors'
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Array
(
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Array
(
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Array
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[patent_title] => 'Isochronous pipelined processor with deterministic control'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901887 | Isochronous pipelined processor with deterministic control | Jul 27, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050027969
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[patent_title] => 'Method for performing single instruction multiple data operations on packed data'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/898590 | Allocating resources to partitions in a partitionable computer | Jul 22, 2004 | Issued |
Array
(
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Array
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Array
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Array
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Array
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Array
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