Search

Robert E. Fennema

Supervisory Patent Examiner (ID: 11059, Phone: (571)272-2748 , Office: P/2126 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2117, 2124, 2126, 2118
Total Applications
376
Issued Applications
186
Pending Applications
14
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4472223 [patent_doc_number] => 07937569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-03 [patent_title] => 'System and method for scheduling operations using speculative data operands' [patent_app_type] => utility [patent_app_number] => 10/839471 [patent_app_country] => US [patent_app_date] => 2004-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 17311 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937569.pdf [firstpage_image] =>[orig_patent_app_number] => 10839471 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/839471
System and method for scheduling operations using speculative data operands May 4, 2004 Issued
Array ( [id] => 7262088 [patent_doc_number] => 20040260911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Unresolved instruction resolution' [patent_app_type] => new [patent_app_number] => 10/831470 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2977 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260911.pdf [firstpage_image] =>[orig_patent_app_number] => 10831470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831470
Unresolved instruction resolution Apr 22, 2004 Abandoned
Array ( [id] => 7047067 [patent_doc_number] => 20050251662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Secondary register file mechanism for virtual multithreading' [patent_app_type] => utility [patent_app_number] => 10/830589 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7287 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20050251662.pdf [firstpage_image] =>[orig_patent_app_number] => 10830589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830589
Secondary register file mechanism for virtual multithreading Apr 21, 2004 Abandoned
Array ( [id] => 7063208 [patent_doc_number] => 20050005084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Scalable processing architecture' [patent_app_type] => utility [patent_app_number] => 10/829668 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5551 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005084.pdf [firstpage_image] =>[orig_patent_app_number] => 10829668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/829668
Scalable processing architecture Apr 21, 2004 Abandoned
Array ( [id] => 7036233 [patent_doc_number] => 20050033945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Dynamically changing the semantic of an instruction' [patent_app_type] => utility [patent_app_number] => 10/830917 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5645 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20050033945.pdf [firstpage_image] =>[orig_patent_app_number] => 10830917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830917
Dynamically changing the semantic of an instruction Apr 21, 2004 Abandoned
Array ( [id] => 922045 [patent_doc_number] => 07325124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'System and method of execution of register pointer instructions ahead of instruction issue' [patent_app_type] => utility [patent_app_number] => 10/828794 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325124.pdf [firstpage_image] =>[orig_patent_app_number] => 10828794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828794
System and method of execution of register pointer instructions ahead of instruction issue Apr 20, 2004 Issued
Array ( [id] => 7091793 [patent_doc_number] => 20050010743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Multiple-thread processor for threaded software applications' [patent_app_type] => utility [patent_app_number] => 10/818785 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21480 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010743.pdf [firstpage_image] =>[orig_patent_app_number] => 10818785 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/818785
Multiple-thread processor for threaded software applications Apr 5, 2004 Abandoned
Array ( [id] => 7266462 [patent_doc_number] => 20040243786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Microprocessor having an extended addressable space' [patent_app_type] => new [patent_app_number] => 10/814823 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4152 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243786.pdf [firstpage_image] =>[orig_patent_app_number] => 10814823 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814823
Microprocessor having an extended addressable space Mar 30, 2004 Issued
Array ( [id] => 6962367 [patent_doc_number] => 20050216713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Instruction text controlled selectively stated branches for prediction via a branch target buffer' [patent_app_type] => utility [patent_app_number] => 10/809749 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4148 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216713.pdf [firstpage_image] =>[orig_patent_app_number] => 10809749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/809749
Instruction text controlled selectively stated branches for prediction via a branch target buffer Mar 24, 2004 Abandoned
Array ( [id] => 7333233 [patent_doc_number] => 20040255097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Instruction encoding within a data processing apparatus having multiple instruction sets' [patent_app_type] => new [patent_app_number] => 10/781883 [patent_app_country] => US [patent_app_date] => 2004-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4624 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20040255097.pdf [firstpage_image] =>[orig_patent_app_number] => 10781883 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781883
Instruction encoding within a data processing apparatus having multiple instruction sets Feb 19, 2004 Issued
Array ( [id] => 7052466 [patent_doc_number] => 20050188185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Method and apparatus for predicate implementation using selective conversion to micro-operations' [patent_app_type] => utility [patent_app_number] => 10/783765 [patent_app_country] => US [patent_app_date] => 2004-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3911 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188185.pdf [firstpage_image] =>[orig_patent_app_number] => 10783765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/783765
Method and apparatus for predicate implementation using selective conversion to micro-operations Feb 19, 2004 Abandoned
Array ( [id] => 4589813 [patent_doc_number] => 07831806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Determining target addresses for instruction flow changing instructions in a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 10/779808 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831806.pdf [firstpage_image] =>[orig_patent_app_number] => 10779808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779808
Determining target addresses for instruction flow changing instructions in a data processing apparatus Feb 17, 2004 Issued
Array ( [id] => 7440419 [patent_doc_number] => 20040162965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Information processing unit' [patent_app_type] => new [patent_app_number] => 10/779801 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3725 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162965.pdf [firstpage_image] =>[orig_patent_app_number] => 10779801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779801
Information processing unit Feb 17, 2004 Abandoned
Array ( [id] => 7384930 [patent_doc_number] => 20040221141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Method for managing a microprocessor stack for saving contextual data' [patent_app_type] => new [patent_app_number] => 10/779855 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4557 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20040221141.pdf [firstpage_image] =>[orig_patent_app_number] => 10779855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779855
Method for managing a microprocessor stack for saving contextual data Feb 16, 2004 Issued
Array ( [id] => 7673641 [patent_doc_number] => 20040128477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Early access to microcode ROM' [patent_app_type] => new [patent_app_number] => 10/735996 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7513 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128477.pdf [firstpage_image] =>[orig_patent_app_number] => 10735996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735996
Early access to microcode ROM Dec 14, 2003 Abandoned
Array ( [id] => 7309434 [patent_doc_number] => 20040117701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Apparatus and method for identification of a primary code start sync point following a return to primary code execution' [patent_app_type] => new [patent_app_number] => 10/729401 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5634 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117701.pdf [firstpage_image] =>[orig_patent_app_number] => 10729401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729401
Apparatus and method for identification of a primary code start sync point following a return to primary code execution Dec 4, 2003 Abandoned
Array ( [id] => 223466 [patent_doc_number] => 07610476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-27 [patent_title] => 'Multiple control sequences per row of microcode ROM' [patent_app_type] => utility [patent_app_number] => 10/729331 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8353 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610476.pdf [firstpage_image] =>[orig_patent_app_number] => 10729331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729331
Multiple control sequences per row of microcode ROM Dec 4, 2003 Issued
Array ( [id] => 472876 [patent_doc_number] => 07234044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'Processor registers having state information' [patent_app_type] => utility [patent_app_number] => 10/727850 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7011 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/234/07234044.pdf [firstpage_image] =>[orig_patent_app_number] => 10727850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/727850
Processor registers having state information Dec 2, 2003 Issued
Array ( [id] => 7557427 [patent_doc_number] => 08069336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Transitioning from instruction cache to trace cache on label boundaries' [patent_app_type] => utility [patent_app_number] => 10/726902 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8142 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069336.pdf [firstpage_image] =>[orig_patent_app_number] => 10726902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726902
Transitioning from instruction cache to trace cache on label boundaries Dec 2, 2003 Issued
Array ( [id] => 6941282 [patent_doc_number] => 20050114845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Device, system and method for detection and handling of misaligned data access' [patent_app_type] => utility [patent_app_number] => 10/721879 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5402 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114845.pdf [firstpage_image] =>[orig_patent_app_number] => 10721879 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721879
Device, system and method for detection and handling of misaligned data access Nov 25, 2003 Issued
Menu